mirror of https://gitee.com/openkylin/linux.git
136 lines
4.3 KiB
Plaintext
136 lines
4.3 KiB
Plaintext
Device tree binding for NVIDIA Tegra XUSB pad controller
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========================================================
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NOTE: It turns out that this binding isn't an accurate description of the XUSB
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pad controller. While the description is good enough for the functional subset
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required for PCIe and SATA, it lacks the flexibility to represent the features
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needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
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The binding described in this file is deprecated and should not be used.
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The Tegra XUSB pad controller manages a set of lanes, each of which can be
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assigned to one out of a set of different pads. Some of these pads have an
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associated PHY that must be powered up before the pad can be used.
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This document defines the device-specific binding for the XUSB pad controller.
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Refer to pinctrl-bindings.txt in this directory for generic information about
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pin controller device tree bindings and ../phy/phy-bindings.txt for details on
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how to describe and reference PHYs in device trees.
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Required properties:
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--------------------
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- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
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Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
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"nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
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- reg: Physical base address and length of the controller's registers.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- padctl
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- #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
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See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values.
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Lane muxing:
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------------
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Child nodes contain the pinmux configurations following the conventions from
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the pinctrl-bindings.txt document. Typically a single, static configuration is
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given and applied at boot time.
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Each subnode describes groups of lanes along with parameters and pads that
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they should be assigned to. The name of these subnodes is not important. All
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subnodes should be parsed solely based on their content.
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Each subnode only applies the parameters that are explicitly listed. In other
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words, if a subnode that lists a function but no pin configuration parameters
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implies no information about any pin configuration parameters. Similarly, a
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subnode that describes only an IDDQ parameter implies no information about
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what function the pins are assigned to. For this reason even seemingly boolean
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values are actually tristates in this binding: unspecified, off or on.
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Unspecified is represented as an absent property, and off/on are represented
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as integer values 0 and 1.
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Required properties:
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- nvidia,lanes: An array of strings. Each string is the name of a lane.
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Optional properties:
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- nvidia,function: A string that is the name of the function (pad) that the
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pin or group should be assigned to. Valid values for function names are
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listed below.
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- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
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Note that not all of these properties are valid for all lanes. Lanes can be
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divided into three groups:
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- otg-0, otg-1, otg-2:
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Valid functions for this group are: "snps", "xusb", "uart", "rsvd".
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The nvidia,iddq property does not apply to this group.
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- ulpi-0, hsic-0, hsic-1:
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Valid functions for this group are: "snps", "xusb".
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The nvidia,iddq property does not apply to this group.
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- pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
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Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".
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Example:
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========
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SoC file extract:
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-----------------
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padctl@7009f000 {
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compatible = "nvidia,tegra124-xusb-padctl";
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reg = <0x0 0x7009f000 0x0 0x1000>;
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resets = <&tegra_car 142>;
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reset-names = "padctl";
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#phy-cells = <1>;
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};
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Board file extract:
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-------------------
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pcie-controller@1003000 {
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...
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phys = <&padctl 0>;
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phy-names = "pcie";
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...
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};
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...
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padctl: padctl@7009f000 {
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pinctrl-0 = <&padctl_default>;
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pinctrl-names = "default";
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padctl_default: pinmux {
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usb3 {
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nvidia,lanes = "pcie-0", "pcie-1";
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nvidia,function = "usb3";
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nvidia,iddq = <0>;
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};
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pcie {
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nvidia,lanes = "pcie-2", "pcie-3",
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"pcie-4";
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nvidia,function = "pcie";
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nvidia,iddq = <0>;
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};
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sata {
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nvidia,lanes = "sata-0";
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nvidia,function = "sata";
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nvidia,iddq = <0>;
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};
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};
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};
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