mirror of https://gitee.com/openkylin/linux.git
438 lines
9.2 KiB
Plaintext
438 lines
9.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/ {
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model = "ARM Versatile AB";
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compatible = "arm,versatile-ab";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&vic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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i2c0 = &i2c0;
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};
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chosen {
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stdout-path = &uart0;
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};
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memory {
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reg = <0x0 0x08000000>;
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};
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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bridge {
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compatible = "ti,ths8134b", "ti,ths8134";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vga_bridge_in: endpoint {
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remote-endpoint = <&clcd_pads_vga_dac>;
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};
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};
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port@1 {
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reg = <1>;
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vga_bridge_out: endpoint {
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remote-endpoint = <&vga_con_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_con_in: endpoint {
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remote-endpoint = <&vga_bridge_out>;
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};
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};
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};
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core-module@10000000 {
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compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
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reg = <0x10000000 0x200>;
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led@08.0 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x01>;
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label = "versatile:0";
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linux,default-trigger = "heartbeat";
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default-state = "on";
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};
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led@08.1 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x02>;
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label = "versatile:1";
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linux,default-trigger = "mmc0";
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default-state = "off";
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};
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led@08.2 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x04>;
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label = "versatile:2";
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linux,default-trigger = "cpu0";
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default-state = "off";
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};
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led@08.3 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x08>;
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label = "versatile:3";
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default-state = "off";
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};
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led@08.4 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x10>;
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label = "versatile:4";
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default-state = "off";
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};
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led@08.5 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x20>;
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label = "versatile:5";
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default-state = "off";
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};
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led@08.6 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x40>;
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label = "versatile:6";
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default-state = "off";
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};
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led@08.7 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x80>;
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label = "versatile:7";
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default-state = "off";
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};
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/* OSC1 on AB, OSC4 on PB */
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osc1: cm_aux_osc@24M {
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#clock-cells = <0>;
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compatible = "arm,versatile-cm-auxosc";
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clocks = <&xtal24mhz>;
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};
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/* The timer clock is the 24 MHz oscillator divided to 1MHz */
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timclk: timclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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pclk: pclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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};
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flash@34000000 {
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/* 64 MiB NOR flash in non-interleaved chips */
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compatible = "arm,versatile-flash", "cfi-flash";
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reg = <0x34000000 0x04000000>;
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bank-width = <4>;
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};
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i2c0: i2c@10002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,versatile-i2c";
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reg = <0x10002000 0x1000>;
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rtc@68 {
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compatible = "dallas,ds1338";
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reg = <0x68>;
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};
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};
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net@10010000 {
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compatible = "smsc,lan91c111";
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reg = <0x10010000 0x10000>;
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interrupts = <25>;
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};
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lcd@10008000 {
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compatible = "arm,versatile-lcd";
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reg = <0x10008000 0x1000>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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vic: intc@10140000 {
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compatible = "arm,versatile-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x10140000 0x1000>;
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clear-mask = <0xffffffff>;
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valid-mask = <0xffffffff>;
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};
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sic: intc@10003000 {
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compatible = "arm,versatile-sic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x10003000 0x1000>;
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interrupt-parent = <&vic>;
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interrupts = <31>; /* Cascaded to vic */
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clear-mask = <0xffffffff>;
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/*
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* Valid interrupt lines mask according to
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* table 4-36 page 4-50 of ARM DUI 0225D
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*/
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valid-mask = <0x0760031b>;
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};
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dma@10130000 {
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compatible = "arm,pl081", "arm,primecell";
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reg = <0x10130000 0x1000>;
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interrupts = <17>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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uart0: uart@101f1000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x101f1000 0x1000>;
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interrupts = <12>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: uart@101f2000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x101f2000 0x1000>;
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interrupts = <13>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart2: uart@101f3000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x101f3000 0x1000>;
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interrupts = <14>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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smc@10100000 {
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compatible = "arm,primecell";
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reg = <0x10100000 0x1000>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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mpmc@10110000 {
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compatible = "arm,primecell";
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reg = <0x10110000 0x1000>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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display@10120000 {
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compatible = "arm,pl110", "arm,primecell";
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reg = <0x10120000 0x1000>;
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interrupts = <16>;
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clocks = <&osc1>, <&pclk>;
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clock-names = "clcdclk", "apb_pclk";
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/* 800x600 16bpp @ 36MHz works fine */
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max-memory-bandwidth = <54000000>;
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/*
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* This port is routed through a PLD (Programmable
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* Logic Device) that routes the output from the CLCD
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* (after transformations) to the VGA DAC and also an
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* external panel connector. The PLD is essential for
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* supporting RGB565/BGR565.
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*
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* The signals from the port thus reaches two endpoints.
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* The PLD is managed through a few special bits in the
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* FPGA "sysreg".
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*
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* This arrangement can be clearly seen in
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* ARM DUI 0225D, page 3-41, figure 3-19.
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*/
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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clcd_pads_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_in>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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clcd_pads_vga_dac: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vga_bridge_in>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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};
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sctl@101e0000 {
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compatible = "arm,primecell";
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reg = <0x101e0000 0x1000>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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watchdog@101e1000 {
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compatible = "arm,primecell";
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reg = <0x101e1000 0x1000>;
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interrupts = <0>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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timer@101e2000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x101e2000 0x1000>;
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interrupts = <4>;
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clocks = <&timclk>, <&timclk>, <&pclk>;
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clock-names = "timer0", "timer1", "apb_pclk";
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};
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timer@101e3000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x101e3000 0x1000>;
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interrupts = <5>;
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clocks = <&timclk>, <&timclk>, <&pclk>;
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clock-names = "timer0", "timer1", "apb_pclk";
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};
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gpio0: gpio@101e4000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x101e4000 0x1000>;
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gpio-controller;
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interrupts = <6>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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gpio1: gpio@101e5000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x101e5000 0x1000>;
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interrupts = <7>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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rtc@101e8000 {
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compatible = "arm,pl030", "arm,primecell";
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reg = <0x101e8000 0x1000>;
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interrupts = <10>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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sci@101f0000 {
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compatible = "arm,primecell";
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reg = <0x101f0000 0x1000>;
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interrupts = <15>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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ssp@101f4000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x101f4000 0x1000>;
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interrupts = <11>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "SSPCLK", "apb_pclk";
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};
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fpga {
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compatible = "arm,versatile-fpga", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10000000 0x10000>;
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sysreg@0 {
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compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
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reg = <0x00000 0x1000>;
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panel: display@0 {
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compatible = "arm,versatile-tft-panel";
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port {
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panel_in: endpoint {
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remote-endpoint = <&clcd_pads_panel>;
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};
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};
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};
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};
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aaci@4000 {
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compatible = "arm,primecell";
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reg = <0x4000 0x1000>;
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interrupts = <24>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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mmc@5000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x5000 0x1000>;
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interrupts-extended = <&vic 22 &sic 1>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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};
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kmi@6000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x6000 0x1000>;
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interrupt-parent = <&sic>;
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interrupts = <3>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@7000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x7000 0x1000>;
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interrupt-parent = <&sic>;
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interrupts = <4>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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};
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};
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};
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