mirror of https://gitee.com/openkylin/linux.git
89 lines
1.5 KiB
Plaintext
89 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014 SUSE LINUX Products GmbH
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*
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* Derived from zynq-zed.dts:
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*
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* Copyright (C) 2011 Xilinx
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* Copyright (C) 2012 National Instruments Corp.
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* Copyright (C) 2013 Xilinx
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*/
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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/ {
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model = "Adapteva Parallella board";
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compatible = "adapteva,parallella", "xlnx,zynq-7000";
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aliases {
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ethernet0 = &gem0;
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serial0 = &uart1;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x40000000>;
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};
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chosen {
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bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
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stdout-path = "serial0:115200n8";
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};
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};
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&clkc {
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fclk-enable = <0xf>;
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ps-clk-frequency = <33333333>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@0 {
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/* Marvell 88E1318 */
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compatible = "ethernet-phy-id0141.0e90",
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"ethernet-phy-ieee802.3-c22";
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reg = <0>;
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device_type = "ethernet-phy";
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marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
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<0x3 0x11 0xfff0 0xa>;
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};
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};
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&i2c0 {
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status = "okay";
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isl9305: isl9305@68 {
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compatible = "isil,isl9305";
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reg = <0x68>;
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regulators {
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dcd1 {
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regulator-name = "VDD_DSP";
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regulator-always-on;
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};
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dcd2 {
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regulator-name = "1P35V";
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regulator-always-on;
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};
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ldo1 {
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regulator-name = "VDD_ADJ";
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};
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ldo2 {
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regulator-name = "VDD_GPIO";
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regulator-always-on;
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};
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};
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};
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};
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&sdhci1 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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