Thara Gopinath 3863c74b51 OMAP3: PM: Fix for MPU power domain MEM BANK position ... MPU power domain bank 0 bits are displayed in position of bank 1 in PWRSTS and PREPWRSTS registers. So read them from correct position Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>		2009-12-11 17:00:42 -07:00
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plat	OMAP3: PM: Fix for MPU power domain MEM BANK position	2009-12-11 17:00:42 -07:00