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#define AR5K_PHY_RESTART_DIV_GC 0x001c0000 is 3 bit wide. The previous values of 0xc and 0x8 are 4bit wide and bigger than the mask. Writing 0 and 1 to AR5K_PHY_RESTART_DIV_GC is consistent with the comments and initvals we have in the HAL. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com> |
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ar9170 | ||
ath5k | ||
ath9k | ||
Kconfig | ||
Makefile | ||
ath.h | ||
debug.c | ||
debug.h | ||
hw.c | ||
main.c | ||
reg.h | ||
regd.c | ||
regd.h | ||
regd_common.h |