mirror of https://gitee.com/openkylin/linux.git
445 lines
13 KiB
C
445 lines
13 KiB
C
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Ben Widawsky <ben@bwidawsk.net>
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*
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/stat.h>
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#include <linux/sysfs.h>
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#include "intel_drv.h"
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#include "i915_drv.h"
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#ifdef CONFIG_PM
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static u32 calc_residency(struct drm_device *dev, const u32 reg)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u64 raw_time; /* 32b value may overflow during fixed point math */
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if (!intel_enable_rc6(dev))
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return 0;
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raw_time = I915_READ(reg) * 128ULL;
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return DIV_ROUND_UP_ULL(raw_time, 100000);
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}
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static ssize_t
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show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
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return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
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}
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static ssize_t
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show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
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u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
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return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
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}
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static ssize_t
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show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
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u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
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return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
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}
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static ssize_t
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show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
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u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
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return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
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}
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static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
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static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
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static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
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static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
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static struct attribute *rc6_attrs[] = {
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&dev_attr_rc6_enable.attr,
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&dev_attr_rc6_residency_ms.attr,
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&dev_attr_rc6p_residency_ms.attr,
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&dev_attr_rc6pp_residency_ms.attr,
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NULL
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};
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static struct attribute_group rc6_attr_group = {
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.name = power_group_name,
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.attrs = rc6_attrs
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};
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#endif
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static int l3_access_valid(struct drm_device *dev, loff_t offset)
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{
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if (!HAS_L3_GPU_CACHE(dev))
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return -EPERM;
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if (offset % 4 != 0)
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return -EINVAL;
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if (offset >= GEN7_L3LOG_SIZE)
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return -ENXIO;
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return 0;
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}
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static ssize_t
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i915_l3_read(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t offset, size_t count)
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{
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struct device *dev = container_of(kobj, struct device, kobj);
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struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
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struct drm_device *drm_dev = dminor->dev;
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struct drm_i915_private *dev_priv = drm_dev->dev_private;
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uint32_t misccpctl;
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int i, ret;
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ret = l3_access_valid(drm_dev, offset);
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if (ret)
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return ret;
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ret = i915_mutex_lock_interruptible(drm_dev);
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if (ret)
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return ret;
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misccpctl = I915_READ(GEN7_MISCCPCTL);
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I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
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for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
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*((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);
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I915_WRITE(GEN7_MISCCPCTL, misccpctl);
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mutex_unlock(&drm_dev->struct_mutex);
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return i - offset;
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}
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static ssize_t
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i915_l3_write(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t offset, size_t count)
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{
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struct device *dev = container_of(kobj, struct device, kobj);
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struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
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struct drm_device *drm_dev = dminor->dev;
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struct drm_i915_private *dev_priv = drm_dev->dev_private;
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u32 *temp = NULL; /* Just here to make handling failures easy */
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int ret;
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ret = l3_access_valid(drm_dev, offset);
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if (ret)
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return ret;
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ret = i915_mutex_lock_interruptible(drm_dev);
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if (ret)
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return ret;
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if (!dev_priv->l3_parity.remap_info) {
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temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
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if (!temp) {
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mutex_unlock(&drm_dev->struct_mutex);
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return -ENOMEM;
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}
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}
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ret = i915_gpu_idle(drm_dev);
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if (ret) {
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kfree(temp);
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mutex_unlock(&drm_dev->struct_mutex);
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return ret;
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}
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/* TODO: Ideally we really want a GPU reset here to make sure errors
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* aren't propagated. Since I cannot find a stable way to reset the GPU
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* at this point it is left as a TODO.
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*/
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if (temp)
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dev_priv->l3_parity.remap_info = temp;
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memcpy(dev_priv->l3_parity.remap_info + (offset/4),
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buf + (offset/4),
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count);
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i915_gem_l3_remap(drm_dev);
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mutex_unlock(&drm_dev->struct_mutex);
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return count;
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}
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static struct bin_attribute dpf_attrs = {
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.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
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.size = GEN7_L3LOG_SIZE,
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.read = i915_l3_read,
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.write = i915_l3_write,
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.mmap = NULL
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};
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static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
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struct device_attribute *attr, char *buf)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv->dev)) {
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u32 freq;
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freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
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ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
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} else {
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ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
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}
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mutex_unlock(&dev_priv->rps.hw_lock);
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return snprintf(buf, PAGE_SIZE, "%d\n", ret);
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}
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static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv->dev))
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ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
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else
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ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
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mutex_unlock(&dev_priv->rps.hw_lock);
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return snprintf(buf, PAGE_SIZE, "%d\n", ret);
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}
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static ssize_t gt_max_freq_mhz_store(struct device *kdev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
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ssize_t ret;
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ret = kstrtou32(buf, 0, &val);
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if (ret)
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return ret;
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv->dev)) {
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val = vlv_freq_opcode(dev_priv->mem_freq, val);
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hw_max = valleyview_rps_max_freq(dev_priv);
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hw_min = valleyview_rps_min_freq(dev_priv);
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non_oc_max = hw_max;
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} else {
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val /= GT_FREQUENCY_MULTIPLIER;
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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hw_max = dev_priv->rps.hw_max;
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non_oc_max = (rp_state_cap & 0xff);
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hw_min = ((rp_state_cap & 0xff0000) >> 16);
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}
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if (val < hw_min || val > hw_max ||
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val < dev_priv->rps.min_delay) {
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mutex_unlock(&dev_priv->rps.hw_lock);
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return -EINVAL;
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}
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if (val > non_oc_max)
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DRM_DEBUG("User requested overclocking to %d\n",
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val * GT_FREQUENCY_MULTIPLIER);
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if (dev_priv->rps.cur_delay > val) {
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if (IS_VALLEYVIEW(dev_priv->dev))
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valleyview_set_rps(dev_priv->dev, val);
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else
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gen6_set_rps(dev_priv->dev, val);
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}
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dev_priv->rps.max_delay = val;
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mutex_unlock(&dev_priv->rps.hw_lock);
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return count;
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}
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static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev_priv->dev))
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ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
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else
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ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
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mutex_unlock(&dev_priv->rps.hw_lock);
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return snprintf(buf, PAGE_SIZE, "%d\n", ret);
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}
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static ssize_t gt_min_freq_mhz_store(struct device *kdev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val, rp_state_cap, hw_max, hw_min;
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ssize_t ret;
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ret = kstrtou32(buf, 0, &val);
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if (ret)
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return ret;
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mutex_lock(&dev_priv->rps.hw_lock);
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if (IS_VALLEYVIEW(dev)) {
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val = vlv_freq_opcode(dev_priv->mem_freq, val);
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hw_max = valleyview_rps_max_freq(dev_priv);
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hw_min = valleyview_rps_min_freq(dev_priv);
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} else {
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val /= GT_FREQUENCY_MULTIPLIER;
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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hw_max = dev_priv->rps.hw_max;
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hw_min = ((rp_state_cap & 0xff0000) >> 16);
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}
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if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
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mutex_unlock(&dev_priv->rps.hw_lock);
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return -EINVAL;
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}
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if (dev_priv->rps.cur_delay < val) {
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if (IS_VALLEYVIEW(dev))
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valleyview_set_rps(dev, val);
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else
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gen6_set_rps(dev_priv->dev, val);
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}
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dev_priv->rps.min_delay = val;
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mutex_unlock(&dev_priv->rps.hw_lock);
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return count;
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}
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static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
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static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
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static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
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static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
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static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
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static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
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static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
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/* For now we have a static number of RP states */
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static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
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{
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struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
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struct drm_device *dev = minor->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val, rp_state_cap;
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ssize_t ret;
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ret = mutex_lock_interruptible(&dev->struct_mutex);
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if (ret)
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return ret;
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rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
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mutex_unlock(&dev->struct_mutex);
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if (attr == &dev_attr_gt_RP0_freq_mhz) {
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val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
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} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
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val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
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} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
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val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
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} else {
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BUG();
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}
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return snprintf(buf, PAGE_SIZE, "%d\n", val);
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}
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static const struct attribute *gen6_attrs[] = {
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&dev_attr_gt_cur_freq_mhz.attr,
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&dev_attr_gt_max_freq_mhz.attr,
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&dev_attr_gt_min_freq_mhz.attr,
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&dev_attr_gt_RP0_freq_mhz.attr,
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&dev_attr_gt_RP1_freq_mhz.attr,
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&dev_attr_gt_RPn_freq_mhz.attr,
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NULL,
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};
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void i915_setup_sysfs(struct drm_device *dev)
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{
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int ret;
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#ifdef CONFIG_PM
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if (INTEL_INFO(dev)->gen >= 6) {
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ret = sysfs_merge_group(&dev->primary->kdev.kobj,
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&rc6_attr_group);
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if (ret)
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DRM_ERROR("RC6 residency sysfs setup failed\n");
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}
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#endif
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if (HAS_L3_GPU_CACHE(dev)) {
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ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
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if (ret)
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DRM_ERROR("l3 parity sysfs setup failed\n");
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}
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if (INTEL_INFO(dev)->gen >= 6) {
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ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
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if (ret)
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DRM_ERROR("gen6 sysfs setup failed\n");
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}
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}
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void i915_teardown_sysfs(struct drm_device *dev)
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{
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sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
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device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
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#ifdef CONFIG_PM
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sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
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#endif
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}
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