mirror of https://gitee.com/openkylin/linux.git
769 lines
30 KiB
C
769 lines
30 KiB
C
/*
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* core.h - DesignWare HS OTG Controller common declarations
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DWC2_CORE_H__
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#define __DWC2_CORE_H__
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#include <linux/usb/phy.h>
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#include "hw.h"
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#ifdef DWC2_LOG_WRITES
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static inline void do_write(u32 value, void *addr)
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{
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writel(value, addr);
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pr_info("INFO:: wrote %08x to %p\n", value, addr);
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}
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#undef writel
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#define writel(v, a) do_write(v, a)
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#endif
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/* Maximum number of Endpoints/HostChannels */
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#define MAX_EPS_CHANNELS 16
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struct dwc2_hsotg;
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struct dwc2_host_chan;
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/* Device States */
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enum dwc2_lx_state {
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DWC2_L0, /* On state */
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DWC2_L1, /* LPM sleep state */
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DWC2_L2, /* USB suspend state */
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DWC2_L3, /* Off state */
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};
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/**
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* struct dwc2_core_params - Parameters for configuring the core
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*
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* @otg_cap: Specifies the OTG capabilities.
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* 0 - HNP and SRP capable
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* 1 - SRP Only capable
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* 2 - No HNP/SRP capable (always available)
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* Defaults to best available option (0, 1, then 2)
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* @otg_ver: OTG version supported
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* 0 - 1.3 (default)
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* 1 - 2.0
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* @dma_enable: Specifies whether to use slave or DMA mode for accessing
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* the data FIFOs. The driver will automatically detect the
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* value for this parameter if none is specified.
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* 0 - Slave (always available)
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* 1 - DMA (default, if available)
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* @dma_desc_enable: When DMA mode is enabled, specifies whether to use
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* address DMA mode or descriptor DMA mode for accessing
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* the data FIFOs. The driver will automatically detect the
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* value for this if none is specified.
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* 0 - Address DMA
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* 1 - Descriptor DMA (default, if available)
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* @speed: Specifies the maximum speed of operation in host and
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* device mode. The actual speed depends on the speed of
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* the attached device and the value of phy_type.
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* 0 - High Speed
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* (default when phy_type is UTMI+ or ULPI)
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* 1 - Full Speed
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* (default when phy_type is Full Speed)
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* @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
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* 1 - Allow dynamic FIFO sizing (default, if available)
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* @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
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* are enabled
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* @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
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* dynamic FIFO sizing is enabled
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* 16 to 32768
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* Actual maximum value is autodetected and also
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* the default.
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* @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
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* in host mode when dynamic FIFO sizing is enabled
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* 16 to 32768
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* Actual maximum value is autodetected and also
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* the default.
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* @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
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* host mode when dynamic FIFO sizing is enabled
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* 16 to 32768
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* Actual maximum value is autodetected and also
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* the default.
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* @max_transfer_size: The maximum transfer size supported, in bytes
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* 2047 to 65,535
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* Actual maximum value is autodetected and also
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* the default.
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* @max_packet_count: The maximum number of packets in a transfer
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* 15 to 511
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* Actual maximum value is autodetected and also
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* the default.
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* @host_channels: The number of host channel registers to use
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* 1 to 16
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* Actual maximum value is autodetected and also
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* the default.
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* @phy_type: Specifies the type of PHY interface to use. By default,
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* the driver will automatically detect the phy_type.
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* 0 - Full Speed Phy
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* 1 - UTMI+ Phy
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* 2 - ULPI Phy
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* Defaults to best available option (2, 1, then 0)
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* @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
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* is applicable for a phy_type of UTMI+ or ULPI. (For a
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* ULPI phy_type, this parameter indicates the data width
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* between the MAC and the ULPI Wrapper.) Also, this
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* parameter is applicable only if the OTG_HSPHY_WIDTH cC
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* parameter was set to "8 and 16 bits", meaning that the
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* core has been configured to work at either data path
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* width.
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* 8 or 16 (default 16 if available)
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* @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
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* data rate. This parameter is only applicable if phy_type
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* is ULPI.
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* 0 - single data rate ULPI interface with 8 bit wide
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* data bus (default)
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* 1 - double data rate ULPI interface with 4 bit wide
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* data bus
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* @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
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* external supply to drive the VBus
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* 0 - Internal supply (default)
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* 1 - External supply
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* @i2c_enable: Specifies whether to use the I2Cinterface for a full
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* speed PHY. This parameter is only applicable if phy_type
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* is FS.
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* 0 - No (default)
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* 1 - Yes
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* @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
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* 0 - No (default)
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* 1 - Yes
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* @host_support_fs_ls_low_power: Specifies whether low power mode is supported
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* when attached to a Full Speed or Low Speed device in
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* host mode.
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* 0 - Don't support low power mode (default)
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* 1 - Support low power mode
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* @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
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* when connected to a Low Speed device in host
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* mode. This parameter is applicable only if
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* host_support_fs_ls_low_power is enabled.
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* 0 - 48 MHz
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* (default when phy_type is UTMI+ or ULPI)
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* 1 - 6 MHz
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* (default when phy_type is Full Speed)
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* @ts_dline: Enable Term Select Dline pulsing
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* 0 - No (default)
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* 1 - Yes
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* @reload_ctl: Allow dynamic reloading of HFIR register during runtime
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* 0 - No (default for core < 2.92a)
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* 1 - Yes (default for core >= 2.92a)
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* @ahbcfg: This field allows the default value of the GAHBCFG
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* register to be overridden
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* -1 - GAHBCFG value will be set to 0x06
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* (INCR4, default)
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* all others - GAHBCFG value will be overridden with
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* this value
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* Not all bits can be controlled like this, the
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* bits defined by GAHBCFG_CTRL_MASK are controlled
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* by the driver and are ignored in this
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* configuration value.
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* @uframe_sched: True to enable the microframe scheduler
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*
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* The following parameters may be specified when starting the module. These
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* parameters define how the DWC_otg controller should be configured. A
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* value of -1 (or any other out of range value) for any parameter means
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* to read the value from hardware (if possible) or use the builtin
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* default described above.
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*/
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struct dwc2_core_params {
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/*
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* Don't add any non-int members here, this will break
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* dwc2_set_all_params!
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*/
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int otg_cap;
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int otg_ver;
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int dma_enable;
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int dma_desc_enable;
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int speed;
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int enable_dynamic_fifo;
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int en_multiple_tx_fifo;
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int host_rx_fifo_size;
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int host_nperio_tx_fifo_size;
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int host_perio_tx_fifo_size;
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int max_transfer_size;
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int max_packet_count;
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int host_channels;
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int phy_type;
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int phy_utmi_width;
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int phy_ulpi_ddr;
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int phy_ulpi_ext_vbus;
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int i2c_enable;
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int ulpi_fs_ls;
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int host_support_fs_ls_low_power;
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int host_ls_low_power_phy_clk;
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int ts_dline;
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int reload_ctl;
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int ahbcfg;
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int uframe_sched;
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};
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/**
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* struct dwc2_hw_params - Autodetected parameters.
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*
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* These parameters are the various parameters read from hardware
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* registers during initialization. They typically contain the best
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* supported or maximum value that can be configured in the
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* corresponding dwc2_core_params value.
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*
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* The values that are not in dwc2_core_params are documented below.
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*
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* @op_mode Mode of Operation
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* 0 - HNP- and SRP-Capable OTG (Host & Device)
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* 1 - SRP-Capable OTG (Host & Device)
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* 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
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* 3 - SRP-Capable Device
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* 4 - Non-OTG Device
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* 5 - SRP-Capable Host
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* 6 - Non-OTG Host
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* @arch Architecture
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* 0 - Slave only
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* 1 - External DMA
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* 2 - Internal DMA
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* @power_optimized Are power optimizations enabled?
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* @num_dev_ep Number of device endpoints available
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* @num_dev_perio_in_ep Number of device periodic IN endpoints
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* avaialable
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* @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
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* Depth
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* 0 to 30
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* @host_perio_tx_q_depth
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* Host Mode Periodic Request Queue Depth
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* 2, 4 or 8
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* @nperio_tx_q_depth
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* Non-Periodic Request Queue Depth
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* 2, 4 or 8
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* @hs_phy_type High-speed PHY interface type
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* 0 - High-speed interface not supported
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* 1 - UTMI+
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* 2 - ULPI
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* 3 - UTMI+ and ULPI
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* @fs_phy_type Full-speed PHY interface type
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* 0 - Full speed interface not supported
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* 1 - Dedicated full speed interface
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* 2 - FS pins shared with UTMI+ pins
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* 3 - FS pins shared with ULPI pins
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* @total_fifo_size: Total internal RAM for FIFOs (bytes)
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* @utmi_phy_data_width UTMI+ PHY data width
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* 0 - 8 bits
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* 1 - 16 bits
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* 2 - 8 or 16 bits
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* @snpsid: Value from SNPSID register
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*/
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struct dwc2_hw_params {
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unsigned op_mode:3;
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unsigned arch:2;
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unsigned dma_desc_enable:1;
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unsigned enable_dynamic_fifo:1;
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unsigned en_multiple_tx_fifo:1;
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unsigned host_rx_fifo_size:16;
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unsigned host_nperio_tx_fifo_size:16;
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unsigned host_perio_tx_fifo_size:16;
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unsigned nperio_tx_q_depth:3;
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unsigned host_perio_tx_q_depth:3;
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unsigned dev_token_q_depth:5;
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unsigned max_transfer_size:26;
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unsigned max_packet_count:11;
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unsigned host_channels:5;
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unsigned hs_phy_type:2;
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unsigned fs_phy_type:2;
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unsigned i2c_enable:1;
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unsigned num_dev_ep:4;
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unsigned num_dev_perio_in_ep:4;
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unsigned total_fifo_size:16;
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unsigned power_optimized:1;
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unsigned utmi_phy_data_width:2;
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u32 snpsid;
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};
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/**
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* struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
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* and periodic schedules
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*
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* @dev: The struct device pointer
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* @regs: Pointer to controller regs
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* @core_params: Parameters that define how the core should be configured
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* @hw_params: Parameters that were autodetected from the
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* hardware registers
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* @op_state: The operational State, during transitions (a_host=>
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* a_peripheral and b_device=>b_host) this may not match
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* the core, but allows the software to determine
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* transitions
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* @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
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* transfer are in process of being queued
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* @srp_success: Stores status of SRP request in the case of a FS PHY
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* with an I2C interface
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* @wq_otg: Workqueue object used for handling of some interrupts
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* @wf_otg: Work object for handling Connector ID Status Change
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* interrupt
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* @wkp_timer: Timer object for handling Wakeup Detected interrupt
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* @lx_state: Lx state of connected device
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* @flags: Flags for handling root port state changes
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* @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
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* Transfers associated with these QHs are not currently
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* assigned to a host channel.
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* @non_periodic_sched_active: Active QHs in the non-periodic schedule.
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* Transfers associated with these QHs are currently
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* assigned to a host channel.
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* @non_periodic_qh_ptr: Pointer to next QH to process in the active
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* non-periodic schedule
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* @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
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* list of QHs for periodic transfers that are _not_
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* scheduled for the next frame. Each QH in the list has an
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* interval counter that determines when it needs to be
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* scheduled for execution. This scheduling mechanism
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* allows only a simple calculation for periodic bandwidth
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* used (i.e. must assume that all periodic transfers may
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* need to execute in the same frame). However, it greatly
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* simplifies scheduling and should be sufficient for the
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* vast majority of OTG hosts, which need to connect to a
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* small number of peripherals at one time. Items move from
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* this list to periodic_sched_ready when the QH interval
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* counter is 0 at SOF.
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* @periodic_sched_ready: List of periodic QHs that are ready for execution in
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* the next frame, but have not yet been assigned to host
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* channels. Items move from this list to
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* periodic_sched_assigned as host channels become
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* available during the current frame.
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* @periodic_sched_assigned: List of periodic QHs to be executed in the next
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* frame that are assigned to host channels. Items move
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* from this list to periodic_sched_queued as the
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* transactions for the QH are queued to the DWC_otg
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* controller.
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* @periodic_sched_queued: List of periodic QHs that have been queued for
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* execution. Items move from this list to either
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* periodic_sched_inactive or periodic_sched_ready when the
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* channel associated with the transfer is released. If the
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* interval for the QH is 1, the item moves to
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* periodic_sched_ready because it must be rescheduled for
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* the next frame. Otherwise, the item moves to
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* periodic_sched_inactive.
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* @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
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* This value is in microseconds per (micro)frame. The
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* assumption is that all periodic transfers may occur in
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* the same (micro)frame.
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* @frame_usecs: Internal variable used by the microframe scheduler
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* @frame_number: Frame number read from the core at SOF. The value ranges
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* from 0 to HFNUM_MAX_FRNUM.
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* @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
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* SOF enable/disable.
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* @free_hc_list: Free host channels in the controller. This is a list of
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* struct dwc2_host_chan items.
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* @periodic_channels: Number of host channels assigned to periodic transfers.
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* Currently assuming that there is a dedicated host
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* channel for each periodic transaction and at least one
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* host channel is available for non-periodic transactions.
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* @non_periodic_channels: Number of host channels assigned to non-periodic
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* transfers
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* @available_host_channels Number of host channels available for the microframe
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* scheduler to use
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* @hc_ptr_array: Array of pointers to the host channel descriptors.
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* Allows accessing a host channel descriptor given the
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* host channel number. This is useful in interrupt
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* handlers.
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* @status_buf: Buffer used for data received during the status phase of
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* a control transfer.
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* @status_buf_dma: DMA address for status_buf
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* @start_work: Delayed work for handling host A-cable connection
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* @reset_work: Delayed work for handling a port reset
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* @lock: Spinlock that protects all the driver data structures
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* @priv: Stores a pointer to the struct usb_hcd
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* @otg_port: OTG port number
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* @frame_list: Frame list
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* @frame_list_dma: Frame list DMA address
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*/
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struct dwc2_hsotg {
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struct device *dev;
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void __iomem *regs;
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/** Params detected from hardware */
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struct dwc2_hw_params hw_params;
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/** Params to actually use */
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struct dwc2_core_params *core_params;
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enum usb_otg_state op_state;
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unsigned int queuing_high_bandwidth:1;
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unsigned int srp_success:1;
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struct workqueue_struct *wq_otg;
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struct work_struct wf_otg;
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struct timer_list wkp_timer;
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enum dwc2_lx_state lx_state;
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union dwc2_hcd_internal_flags {
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u32 d32;
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struct {
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unsigned port_connect_status_change:1;
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unsigned port_connect_status:1;
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unsigned port_reset_change:1;
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unsigned port_enable_change:1;
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unsigned port_suspend_change:1;
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unsigned port_over_current_change:1;
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unsigned port_l1_change:1;
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unsigned reserved:26;
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} b;
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} flags;
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struct list_head non_periodic_sched_inactive;
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struct list_head non_periodic_sched_active;
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struct list_head *non_periodic_qh_ptr;
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struct list_head periodic_sched_inactive;
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struct list_head periodic_sched_ready;
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struct list_head periodic_sched_assigned;
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struct list_head periodic_sched_queued;
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u16 periodic_usecs;
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u16 frame_usecs[8];
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u16 frame_number;
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u16 periodic_qh_count;
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|
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#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
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#define FRAME_NUM_ARRAY_SIZE 1000
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u16 last_frame_num;
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u16 *frame_num_array;
|
|
u16 *last_frame_num_array;
|
|
int frame_num_idx;
|
|
int dumped_frame_num_array;
|
|
#endif
|
|
|
|
struct list_head free_hc_list;
|
|
int periodic_channels;
|
|
int non_periodic_channels;
|
|
int available_host_channels;
|
|
struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
|
|
u8 *status_buf;
|
|
dma_addr_t status_buf_dma;
|
|
#define DWC2_HCD_STATUS_BUF_SIZE 64
|
|
|
|
struct delayed_work start_work;
|
|
struct delayed_work reset_work;
|
|
spinlock_t lock;
|
|
void *priv;
|
|
u8 otg_port;
|
|
u32 *frame_list;
|
|
dma_addr_t frame_list_dma;
|
|
|
|
/* DWC OTG HW Release versions */
|
|
#define DWC2_CORE_REV_2_71a 0x4f54271a
|
|
#define DWC2_CORE_REV_2_90a 0x4f54290a
|
|
#define DWC2_CORE_REV_2_92a 0x4f54292a
|
|
#define DWC2_CORE_REV_2_94a 0x4f54294a
|
|
#define DWC2_CORE_REV_3_00a 0x4f54300a
|
|
|
|
#ifdef DEBUG
|
|
u32 frrem_samples;
|
|
u64 frrem_accum;
|
|
|
|
u32 hfnum_7_samples_a;
|
|
u64 hfnum_7_frrem_accum_a;
|
|
u32 hfnum_0_samples_a;
|
|
u64 hfnum_0_frrem_accum_a;
|
|
u32 hfnum_other_samples_a;
|
|
u64 hfnum_other_frrem_accum_a;
|
|
|
|
u32 hfnum_7_samples_b;
|
|
u64 hfnum_7_frrem_accum_b;
|
|
u32 hfnum_0_samples_b;
|
|
u64 hfnum_0_frrem_accum_b;
|
|
u32 hfnum_other_samples_b;
|
|
u64 hfnum_other_frrem_accum_b;
|
|
#endif
|
|
};
|
|
|
|
/* Reasons for halting a host channel */
|
|
enum dwc2_halt_status {
|
|
DWC2_HC_XFER_NO_HALT_STATUS,
|
|
DWC2_HC_XFER_COMPLETE,
|
|
DWC2_HC_XFER_URB_COMPLETE,
|
|
DWC2_HC_XFER_ACK,
|
|
DWC2_HC_XFER_NAK,
|
|
DWC2_HC_XFER_NYET,
|
|
DWC2_HC_XFER_STALL,
|
|
DWC2_HC_XFER_XACT_ERR,
|
|
DWC2_HC_XFER_FRAME_OVERRUN,
|
|
DWC2_HC_XFER_BABBLE_ERR,
|
|
DWC2_HC_XFER_DATA_TOGGLE_ERR,
|
|
DWC2_HC_XFER_AHB_ERR,
|
|
DWC2_HC_XFER_PERIODIC_INCOMPLETE,
|
|
DWC2_HC_XFER_URB_DEQUEUE,
|
|
};
|
|
|
|
/*
|
|
* The following functions support initialization of the core driver component
|
|
* and the DWC_otg controller
|
|
*/
|
|
extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
|
|
|
|
/*
|
|
* Host core Functions.
|
|
* The following functions support managing the DWC_otg controller in host
|
|
* mode.
|
|
*/
|
|
extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
|
|
extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
|
|
enum dwc2_halt_status halt_status);
|
|
extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_host_chan *chan);
|
|
extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_host_chan *chan);
|
|
extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_host_chan *chan);
|
|
extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_host_chan *chan);
|
|
extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
|
|
struct dwc2_host_chan *chan);
|
|
extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
|
|
extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
|
|
|
|
extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
|
|
extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
|
|
|
|
/*
|
|
* Common core Functions.
|
|
* The following functions support managing the DWC_otg controller in either
|
|
* device or host mode.
|
|
*/
|
|
extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
|
|
extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
|
|
extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
|
|
|
|
extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq);
|
|
extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
|
|
extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
|
|
|
|
/* This function should be called on every hardware interrupt. */
|
|
extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
|
|
|
|
/* OTG Core Parameters */
|
|
|
|
/*
|
|
* Specifies the OTG capabilities. The driver will automatically
|
|
* detect the value for this parameter if none is specified.
|
|
* 0 - HNP and SRP capable (default)
|
|
* 1 - SRP Only capable
|
|
* 2 - No HNP/SRP capable
|
|
*/
|
|
extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
|
|
#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
|
|
#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
|
|
#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
|
|
|
|
/*
|
|
* Specifies whether to use slave or DMA mode for accessing the data
|
|
* FIFOs. The driver will automatically detect the value for this
|
|
* parameter if none is specified.
|
|
* 0 - Slave
|
|
* 1 - DMA (default, if available)
|
|
*/
|
|
extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* When DMA mode is enabled specifies whether to use
|
|
* address DMA or DMA Descritor mode for accessing the data
|
|
* FIFOs in device mode. The driver will automatically detect
|
|
* the value for this parameter if none is specified.
|
|
* 0 - address DMA
|
|
* 1 - DMA Descriptor(default, if available)
|
|
*/
|
|
extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* Specifies the maximum speed of operation in host and device mode.
|
|
* The actual speed depends on the speed of the attached device and
|
|
* the value of phy_type. The actual speed depends on the speed of the
|
|
* attached device.
|
|
* 0 - High Speed (default)
|
|
* 1 - Full Speed
|
|
*/
|
|
extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
|
|
#define DWC2_SPEED_PARAM_HIGH 0
|
|
#define DWC2_SPEED_PARAM_FULL 1
|
|
|
|
/*
|
|
* Specifies whether low power mode is supported when attached
|
|
* to a Full Speed or Low Speed device in host mode.
|
|
*
|
|
* 0 - Don't support low power mode (default)
|
|
* 1 - Support low power mode
|
|
*/
|
|
extern void dwc2_set_param_host_support_fs_ls_low_power(
|
|
struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* Specifies the PHY clock rate in low power mode when connected to a
|
|
* Low Speed device in host mode. This parameter is applicable only if
|
|
* HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
|
|
* then defaults to 6 MHZ otherwise 48 MHZ.
|
|
*
|
|
* 0 - 48 MHz
|
|
* 1 - 6 MHz
|
|
*/
|
|
extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
|
|
int val);
|
|
#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
|
|
#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
|
|
|
|
/*
|
|
* 0 - Use cC FIFO size parameters
|
|
* 1 - Allow dynamic FIFO sizing (default)
|
|
*/
|
|
extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
|
|
int val);
|
|
|
|
/*
|
|
* Number of 4-byte words in the Rx FIFO in host mode when dynamic
|
|
* FIFO sizing is enabled.
|
|
* 16 to 32768 (default 1024)
|
|
*/
|
|
extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* Number of 4-byte words in the non-periodic Tx FIFO in host mode
|
|
* when Dynamic FIFO sizing is enabled in the core.
|
|
* 16 to 32768 (default 256)
|
|
*/
|
|
extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
|
|
int val);
|
|
|
|
/*
|
|
* Number of 4-byte words in the host periodic Tx FIFO when dynamic
|
|
* FIFO sizing is enabled.
|
|
* 16 to 32768 (default 256)
|
|
*/
|
|
extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
|
|
int val);
|
|
|
|
/*
|
|
* The maximum transfer size supported in bytes.
|
|
* 2047 to 65,535 (default 65,535)
|
|
*/
|
|
extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* The maximum number of packets in a transfer.
|
|
* 15 to 511 (default 511)
|
|
*/
|
|
extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* The number of host channel registers to use.
|
|
* 1 to 16 (default 11)
|
|
* Note: The FPGA configuration supports a maximum of 11 host channels.
|
|
*/
|
|
extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* Specifies the type of PHY interface to use. By default, the driver
|
|
* will automatically detect the phy_type.
|
|
*
|
|
* 0 - Full Speed PHY
|
|
* 1 - UTMI+ (default)
|
|
* 2 - ULPI
|
|
*/
|
|
extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
|
|
#define DWC2_PHY_TYPE_PARAM_FS 0
|
|
#define DWC2_PHY_TYPE_PARAM_UTMI 1
|
|
#define DWC2_PHY_TYPE_PARAM_ULPI 2
|
|
|
|
/*
|
|
* Specifies the UTMI+ Data Width. This parameter is
|
|
* applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
|
|
* PHY_TYPE, this parameter indicates the data width between
|
|
* the MAC and the ULPI Wrapper.) Also, this parameter is
|
|
* applicable only if the OTG_HSPHY_WIDTH cC parameter was set
|
|
* to "8 and 16 bits", meaning that the core has been
|
|
* configured to work at either data path width.
|
|
*
|
|
* 8 or 16 bits (default 16)
|
|
*/
|
|
extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* Specifies whether the ULPI operates at double or single
|
|
* data rate. This parameter is only applicable if PHY_TYPE is
|
|
* ULPI.
|
|
*
|
|
* 0 - single data rate ULPI interface with 8 bit wide data
|
|
* bus (default)
|
|
* 1 - double data rate ULPI interface with 4 bit wide data
|
|
* bus
|
|
*/
|
|
extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* Specifies whether to use the internal or external supply to
|
|
* drive the vbus with a ULPI phy.
|
|
*/
|
|
extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
|
|
#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
|
|
#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
|
|
|
|
/*
|
|
* Specifies whether to use the I2Cinterface for full speed PHY. This
|
|
* parameter is only applicable if PHY_TYPE is FS.
|
|
* 0 - No (default)
|
|
* 1 - Yes
|
|
*/
|
|
extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* Specifies whether dedicated transmit FIFOs are
|
|
* enabled for non periodic IN endpoints in device mode
|
|
* 0 - No
|
|
* 1 - Yes
|
|
*/
|
|
extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
|
|
int val);
|
|
|
|
extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
|
|
|
|
/*
|
|
* Dump core registers and SPRAM
|
|
*/
|
|
extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
|
|
extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
|
|
extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
|
|
|
|
/*
|
|
* Return OTG version - either 1.3 or 2.0
|
|
*/
|
|
extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
|
|
|
|
#endif /* __DWC2_CORE_H__ */
|