mirror of https://gitee.com/openkylin/linux.git
154 lines
3.4 KiB
C
154 lines
3.4 KiB
C
/*
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* arch/arm/mach-tegra/include/mach/clock.h
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_CLOCK_H
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#define __MACH_TEGRA_CLOCK_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/list.h>
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#include <mach/clk.h>
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#define DIV_BUS (1 << 0)
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#define DIV_U71 (1 << 1)
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#define DIV_U71_FIXED (1 << 2)
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#define DIV_2 (1 << 3)
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#define DIV_U16 (1 << 4)
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#define PLL_FIXED (1 << 5)
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#define PLL_HAS_CPCON (1 << 6)
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#define MUX (1 << 7)
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#define PLLD (1 << 8)
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#define PERIPH_NO_RESET (1 << 9)
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#define PERIPH_NO_ENB (1 << 10)
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#define PERIPH_EMC_ENB (1 << 11)
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#define PERIPH_MANUAL_RESET (1 << 12)
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#define PLL_ALT_MISC_REG (1 << 13)
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#define PLLU (1 << 14)
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#define PLLX (1 << 15)
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#define MUX_PWM (1 << 16)
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#define MUX8 (1 << 17)
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#define DIV_U71_UART (1 << 18)
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#define MUX_CLK_OUT (1 << 19)
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#define PLLM (1 << 20)
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#define DIV_U71_INT (1 << 21)
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#define DIV_U71_IDLE (1 << 22)
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#define ENABLE_ON_INIT (1 << 28)
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#define PERIPH_ON_APB (1 << 29)
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struct clk_tegra;
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#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
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struct clk_mux_sel {
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struct clk *input;
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u32 value;
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};
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struct clk_pll_freq_table {
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unsigned long input_rate;
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unsigned long output_rate;
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u16 n;
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u16 m;
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u8 p;
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u8 cpcon;
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};
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enum clk_state {
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UNINITIALIZED = 0,
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ON,
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OFF,
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};
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struct clk_tegra {
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/* node for master clocks list */
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struct list_head node; /* node for list of all clocks */
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struct clk_lookup lookup;
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struct clk_hw hw;
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bool set;
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unsigned long fixed_rate;
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unsigned long max_rate;
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unsigned long min_rate;
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u32 flags;
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const char *name;
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enum clk_state state;
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u32 div;
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u32 mul;
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u32 reg;
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u32 reg_shift;
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struct list_head shared_bus_list;
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union {
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struct {
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unsigned int clk_num;
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} periph;
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struct {
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unsigned long input_min;
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unsigned long input_max;
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unsigned long cf_min;
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unsigned long cf_max;
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unsigned long vco_min;
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unsigned long vco_max;
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const struct clk_pll_freq_table *freq_table;
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int lock_delay;
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unsigned long fixed_rate;
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} pll;
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struct {
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u32 sel;
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u32 reg_mask;
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} mux;
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struct {
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struct clk *main;
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struct clk *backup;
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} cpu;
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struct {
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struct list_head node;
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bool enabled;
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unsigned long rate;
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} shared_bus_user;
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} u;
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void (*reset)(struct clk_hw *, bool);
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int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
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};
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struct clk_duplicate {
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const char *name;
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struct clk_lookup lookup;
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};
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struct tegra_clk_init_table {
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const char *name;
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const char *parent;
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unsigned long rate;
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bool enabled;
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};
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void tegra_clk_add(struct clk *c);
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void tegra2_init_clocks(void);
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void tegra30_init_clocks(void);
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struct clk *tegra_get_clock_by_name(const char *name);
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void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
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#endif
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