mirror of https://gitee.com/openkylin/linux.git
936 lines
23 KiB
C
936 lines
23 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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// Copyright(c) 2015-17 Intel Corporation.
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/*
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* Soundwire Intel Master Driver
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*/
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_intel.h>
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#include "cadence_master.h"
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#include "intel.h"
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/* Intel SHIM Registers Definition */
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#define SDW_SHIM_LCAP 0x0
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#define SDW_SHIM_LCTL 0x4
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#define SDW_SHIM_IPPTR 0x8
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#define SDW_SHIM_SYNC 0xC
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#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
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#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
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#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
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#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
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#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
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#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
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#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
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#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
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#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
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#define SDW_SHIM_WAKEEN 0x190
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#define SDW_SHIM_WAKESTS 0x192
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#define SDW_SHIM_LCTL_SPA BIT(0)
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#define SDW_SHIM_LCTL_CPA BIT(8)
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#define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F
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#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
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#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
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#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
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#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
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#define SDW_SHIM_SYNC_SYNCGO BIT(24)
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#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
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#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
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#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
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#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
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#define SDW_SHIM_PCMSYCM_DIR BIT(15)
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#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
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#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
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#define SDW_SHIM_IOCTL_MIF BIT(0)
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#define SDW_SHIM_IOCTL_CO BIT(1)
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#define SDW_SHIM_IOCTL_COE BIT(2)
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#define SDW_SHIM_IOCTL_DO BIT(3)
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#define SDW_SHIM_IOCTL_DOE BIT(4)
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#define SDW_SHIM_IOCTL_BKE BIT(5)
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#define SDW_SHIM_IOCTL_WPDD BIT(6)
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#define SDW_SHIM_IOCTL_CIBD BIT(8)
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#define SDW_SHIM_IOCTL_DIBD BIT(9)
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#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
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#define SDW_SHIM_CTMCTL_DODS BIT(1)
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#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
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#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
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#define SDW_SHIM_WAKESTS_STATUS BIT(0)
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/* Intel ALH Register definitions */
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#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
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#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
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#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
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#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
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enum intel_pdi_type {
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INTEL_PDI_IN = 0,
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INTEL_PDI_OUT = 1,
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INTEL_PDI_BD = 2,
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};
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struct sdw_intel {
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struct sdw_cdns cdns;
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int instance;
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struct sdw_intel_link_res *res;
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};
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#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
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/*
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* Read, write helpers for HW registers
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*/
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static inline int intel_readl(void __iomem *base, int offset)
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{
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return readl(base + offset);
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}
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static inline void intel_writel(void __iomem *base, int offset, int value)
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{
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writel(value, base + offset);
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}
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static inline u16 intel_readw(void __iomem *base, int offset)
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{
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return readw(base + offset);
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}
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static inline void intel_writew(void __iomem *base, int offset, u16 value)
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{
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writew(value, base + offset);
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}
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static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
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{
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int timeout = 10;
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u32 reg_read;
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writel(value, base + offset);
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do {
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reg_read = readl(base + offset);
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if (!(reg_read & mask))
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return 0;
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timeout--;
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udelay(50);
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} while (timeout != 0);
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return -EAGAIN;
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}
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static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
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{
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int timeout = 10;
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u32 reg_read;
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writel(value, base + offset);
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do {
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reg_read = readl(base + offset);
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if (reg_read & mask)
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return 0;
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timeout--;
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udelay(50);
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} while (timeout != 0);
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return -EAGAIN;
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}
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/*
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* shim ops
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*/
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static int intel_link_power_up(struct sdw_intel *sdw)
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{
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unsigned int link_id = sdw->instance;
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void __iomem *shim = sdw->res->shim;
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int spa_mask, cpa_mask;
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int link_control, ret;
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/* Link power up sequence */
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link_control = intel_readl(shim, SDW_SHIM_LCTL);
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spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
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cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
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link_control |= spa_mask;
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ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
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if (ret < 0)
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return ret;
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sdw->cdns.link_up = true;
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return 0;
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}
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static int intel_shim_init(struct sdw_intel *sdw)
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{
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void __iomem *shim = sdw->res->shim;
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unsigned int link_id = sdw->instance;
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int sync_reg, ret;
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u16 ioctl = 0, act = 0;
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/* Initialize Shim */
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ioctl |= SDW_SHIM_IOCTL_BKE;
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl |= SDW_SHIM_IOCTL_WPDD;
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl |= SDW_SHIM_IOCTL_DO;
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl |= SDW_SHIM_IOCTL_DOE;
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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/* Switch to MIP from Glue logic */
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ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
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ioctl &= ~(SDW_SHIM_IOCTL_DOE);
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl &= ~(SDW_SHIM_IOCTL_DO);
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl |= (SDW_SHIM_IOCTL_MIF);
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl &= ~(SDW_SHIM_IOCTL_BKE);
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ioctl &= ~(SDW_SHIM_IOCTL_COE);
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
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act |= SDW_SHIM_CTMCTL_DACTQE;
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act |= SDW_SHIM_CTMCTL_DODS;
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intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
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/* Now set SyncPRD period */
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sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
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sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
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SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
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/* Set SyncCPU bit */
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sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
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ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
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SDW_SHIM_SYNC_SYNCCPU);
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if (ret < 0)
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dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
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return ret;
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}
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/*
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* PDI routines
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*/
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static void intel_pdi_init(struct sdw_intel *sdw,
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struct sdw_cdns_stream_config *config)
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{
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void __iomem *shim = sdw->res->shim;
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unsigned int link_id = sdw->instance;
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int pcm_cap, pdm_cap;
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/* PCM Stream Capability */
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pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
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config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
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config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
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SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
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config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
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dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
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config->pcm_bd, config->pcm_in, config->pcm_out);
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/* PDM Stream Capability */
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pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
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config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
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config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
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SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
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config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
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dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
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config->pdm_bd, config->pdm_in, config->pdm_out);
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}
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static int
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intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
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{
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void __iomem *shim = sdw->res->shim;
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unsigned int link_id = sdw->instance;
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int count;
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if (pcm) {
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count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
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} else {
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count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
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count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
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}
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/* zero based values for channel count in register */
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count++;
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return count;
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}
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static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
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struct sdw_cdns_pdi *pdi,
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unsigned int num_pdi,
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unsigned int *num_ch, bool pcm)
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{
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int i, ch_count = 0;
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for (i = 0; i < num_pdi; i++) {
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pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
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ch_count += pdi->ch_count;
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pdi++;
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}
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*num_ch = ch_count;
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return 0;
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}
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static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
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struct sdw_cdns_streams *stream, bool pcm)
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{
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intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
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&stream->num_ch_bd, pcm);
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intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
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&stream->num_ch_in, pcm);
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intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
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&stream->num_ch_out, pcm);
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return 0;
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}
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static int intel_pdi_ch_update(struct sdw_intel *sdw)
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{
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/* First update PCM streams followed by PDM streams */
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intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
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intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
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return 0;
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}
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static void
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intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
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{
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void __iomem *shim = sdw->res->shim;
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unsigned int link_id = sdw->instance;
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int pdi_conf = 0;
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pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
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/*
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* Program stream parameters to stream SHIM register
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* This is applicable for PCM stream only.
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*/
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if (pdi->type != SDW_STREAM_PCM)
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return;
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if (pdi->dir == SDW_DATA_DIR_RX)
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pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
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else
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pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
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pdi_conf |= (pdi->intel_alh_id <<
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SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
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pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
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pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
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intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
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}
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static void
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intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
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{
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void __iomem *alh = sdw->res->alh;
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unsigned int link_id = sdw->instance;
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unsigned int conf;
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pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
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/* Program Stream config ALH register */
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conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
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conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
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SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
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conf |= ((pdi->ch_count - 1) <<
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SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
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intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
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}
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static int intel_config_stream(struct sdw_intel *sdw,
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struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai,
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struct snd_pcm_hw_params *hw_params, int link_id)
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{
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if (sdw->res->ops && sdw->res->ops->config_stream)
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return sdw->res->ops->config_stream(sdw->res->arg,
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substream, dai, hw_params, link_id);
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return -EIO;
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}
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/*
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* bank switch routines
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*/
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static int intel_pre_bank_switch(struct sdw_bus *bus)
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{
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struct sdw_cdns *cdns = bus_to_cdns(bus);
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struct sdw_intel *sdw = cdns_to_intel(cdns);
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void __iomem *shim = sdw->res->shim;
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int sync_reg;
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/* Write to register only for multi-link */
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if (!bus->multi_link)
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return 0;
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/* Read SYNC register */
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sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
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sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
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intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
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return 0;
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}
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static int intel_post_bank_switch(struct sdw_bus *bus)
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{
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struct sdw_cdns *cdns = bus_to_cdns(bus);
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struct sdw_intel *sdw = cdns_to_intel(cdns);
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void __iomem *shim = sdw->res->shim;
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int sync_reg, ret;
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/* Write to register only for multi-link */
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if (!bus->multi_link)
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return 0;
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/* Read SYNC register */
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sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
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/*
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* post_bank_switch() ops is called from the bus in loop for
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* all the Masters in the steam with the expectation that
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* we trigger the bankswitch for the only first Master in the list
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* and do nothing for the other Masters
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*
|
|
* So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
|
|
*/
|
|
if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
|
|
return 0;
|
|
|
|
/*
|
|
* Set SyncGO bit to synchronously trigger a bank switch for
|
|
* all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
|
|
* the Masters.
|
|
*/
|
|
sync_reg |= SDW_SHIM_SYNC_SYNCGO;
|
|
|
|
ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
|
|
SDW_SHIM_SYNC_SYNCGO);
|
|
if (ret < 0)
|
|
dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* DAI routines
|
|
*/
|
|
|
|
static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw,
|
|
u32 ch, u32 dir, bool pcm)
|
|
{
|
|
struct sdw_cdns *cdns = &sdw->cdns;
|
|
struct sdw_cdns_port *port = NULL;
|
|
int i, ret = 0;
|
|
|
|
for (i = 0; i < cdns->num_ports; i++) {
|
|
if (cdns->ports[i].assigned)
|
|
continue;
|
|
|
|
port = &cdns->ports[i];
|
|
port->assigned = true;
|
|
port->direction = dir;
|
|
port->ch = ch;
|
|
break;
|
|
}
|
|
|
|
if (!port) {
|
|
dev_err(cdns->dev, "Unable to find a free port\n");
|
|
return NULL;
|
|
}
|
|
|
|
if (pcm) {
|
|
ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir);
|
|
if (ret)
|
|
goto out;
|
|
|
|
intel_pdi_shim_configure(sdw, port->pdi);
|
|
sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi);
|
|
|
|
intel_pdi_alh_configure(sdw, port->pdi);
|
|
|
|
} else {
|
|
ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir);
|
|
}
|
|
|
|
out:
|
|
if (ret) {
|
|
port->assigned = false;
|
|
port = NULL;
|
|
}
|
|
|
|
return port;
|
|
}
|
|
|
|
static void intel_port_cleanup(struct sdw_cdns_dma_data *dma)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < dma->nr_ports; i++) {
|
|
if (dma->port[i]) {
|
|
dma->port[i]->pdi->assigned = false;
|
|
dma->port[i]->pdi = NULL;
|
|
dma->port[i]->assigned = false;
|
|
dma->port[i] = NULL;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int intel_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
|
|
struct sdw_intel *sdw = cdns_to_intel(cdns);
|
|
struct sdw_cdns_dma_data *dma;
|
|
struct sdw_stream_config sconfig;
|
|
struct sdw_port_config *pconfig;
|
|
int ret, i, ch, dir;
|
|
bool pcm = true;
|
|
|
|
dma = snd_soc_dai_get_dma_data(dai, substream);
|
|
if (!dma)
|
|
return -EIO;
|
|
|
|
ch = params_channels(params);
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
dir = SDW_DATA_DIR_RX;
|
|
else
|
|
dir = SDW_DATA_DIR_TX;
|
|
|
|
if (dma->stream_type == SDW_STREAM_PDM) {
|
|
/* TODO: Check whether PDM decimator is already in use */
|
|
dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir);
|
|
pcm = false;
|
|
} else {
|
|
dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir);
|
|
}
|
|
|
|
if (!dma->nr_ports) {
|
|
dev_err(dai->dev, "ports/resources not available\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL);
|
|
if (!dma->port)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < dma->nr_ports; i++) {
|
|
dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm);
|
|
if (!dma->port[i]) {
|
|
ret = -EINVAL;
|
|
goto port_error;
|
|
}
|
|
}
|
|
|
|
/* Inform DSP about PDI stream number */
|
|
for (i = 0; i < dma->nr_ports; i++) {
|
|
ret = intel_config_stream(sdw, substream, dai, params,
|
|
dma->port[i]->pdi->intel_alh_id);
|
|
if (ret)
|
|
goto port_error;
|
|
}
|
|
|
|
sconfig.direction = dir;
|
|
sconfig.ch_count = ch;
|
|
sconfig.frame_rate = params_rate(params);
|
|
sconfig.type = dma->stream_type;
|
|
|
|
if (dma->stream_type == SDW_STREAM_PDM) {
|
|
sconfig.frame_rate *= 50;
|
|
sconfig.bps = 1;
|
|
} else {
|
|
sconfig.bps = snd_pcm_format_width(params_format(params));
|
|
}
|
|
|
|
/* Port configuration */
|
|
pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL);
|
|
if (!pconfig) {
|
|
ret = -ENOMEM;
|
|
goto port_error;
|
|
}
|
|
|
|
for (i = 0; i < dma->nr_ports; i++) {
|
|
pconfig[i].num = dma->port[i]->num;
|
|
pconfig[i].ch_mask = (1 << ch) - 1;
|
|
}
|
|
|
|
ret = sdw_stream_add_master(&cdns->bus, &sconfig,
|
|
pconfig, dma->nr_ports, dma->stream);
|
|
if (ret) {
|
|
dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
|
|
goto stream_error;
|
|
}
|
|
|
|
kfree(pconfig);
|
|
return ret;
|
|
|
|
stream_error:
|
|
kfree(pconfig);
|
|
port_error:
|
|
intel_port_cleanup(dma);
|
|
kfree(dma->port);
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
|
|
{
|
|
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
|
|
struct sdw_cdns_dma_data *dma;
|
|
int ret;
|
|
|
|
dma = snd_soc_dai_get_dma_data(dai, substream);
|
|
if (!dma)
|
|
return -EIO;
|
|
|
|
ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
|
|
if (ret < 0)
|
|
dev_err(dai->dev, "remove master from stream %s failed: %d\n",
|
|
dma->stream->name, ret);
|
|
|
|
intel_port_cleanup(dma);
|
|
kfree(dma->port);
|
|
return ret;
|
|
}
|
|
|
|
static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
|
|
void *stream, int direction)
|
|
{
|
|
return cdns_set_sdw_stream(dai, stream, true, direction);
|
|
}
|
|
|
|
static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
|
|
void *stream, int direction)
|
|
{
|
|
return cdns_set_sdw_stream(dai, stream, false, direction);
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
|
|
.hw_params = intel_hw_params,
|
|
.hw_free = intel_hw_free,
|
|
.shutdown = sdw_cdns_shutdown,
|
|
.set_sdw_stream = intel_pcm_set_sdw_stream,
|
|
};
|
|
|
|
static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
|
|
.hw_params = intel_hw_params,
|
|
.hw_free = intel_hw_free,
|
|
.shutdown = sdw_cdns_shutdown,
|
|
.set_sdw_stream = intel_pdm_set_sdw_stream,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver dai_component = {
|
|
.name = "soundwire",
|
|
};
|
|
|
|
static int intel_create_dai(struct sdw_cdns *cdns,
|
|
struct snd_soc_dai_driver *dais,
|
|
enum intel_pdi_type type,
|
|
u32 num, u32 off, u32 max_ch, bool pcm)
|
|
{
|
|
int i;
|
|
|
|
if (num == 0)
|
|
return 0;
|
|
|
|
/* TODO: Read supported rates/formats from hardware */
|
|
for (i = off; i < (off + num); i++) {
|
|
dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
|
|
cdns->instance, i);
|
|
if (!dais[i].name)
|
|
return -ENOMEM;
|
|
|
|
if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
|
|
dais[i].playback.stream_name =
|
|
kasprintf(GFP_KERNEL, "SDW%d Tx%d",
|
|
cdns->instance, i);
|
|
if (!dais[i].playback.stream_name) {
|
|
kfree(dais[i].name);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dais[i].playback.channels_min = 1;
|
|
dais[i].playback.channels_max = max_ch;
|
|
dais[i].playback.rates = SNDRV_PCM_RATE_48000;
|
|
dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
|
|
}
|
|
|
|
if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
|
|
dais[i].capture.stream_name =
|
|
kasprintf(GFP_KERNEL, "SDW%d Rx%d",
|
|
cdns->instance, i);
|
|
if (!dais[i].capture.stream_name) {
|
|
kfree(dais[i].name);
|
|
kfree(dais[i].playback.stream_name);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dais[i].capture.channels_min = 1;
|
|
dais[i].capture.channels_max = max_ch;
|
|
dais[i].capture.rates = SNDRV_PCM_RATE_48000;
|
|
dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
|
|
}
|
|
|
|
dais[i].id = SDW_DAI_ID_RANGE_START + i;
|
|
|
|
if (pcm)
|
|
dais[i].ops = &intel_pcm_dai_ops;
|
|
else
|
|
dais[i].ops = &intel_pdm_dai_ops;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_register_dai(struct sdw_intel *sdw)
|
|
{
|
|
struct sdw_cdns *cdns = &sdw->cdns;
|
|
struct sdw_cdns_streams *stream;
|
|
struct snd_soc_dai_driver *dais;
|
|
int num_dai, ret, off = 0;
|
|
|
|
/* DAIs are created based on total number of PDIs supported */
|
|
num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
|
|
|
|
dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
|
|
if (!dais)
|
|
return -ENOMEM;
|
|
|
|
/* Create PCM DAIs */
|
|
stream = &cdns->pcm;
|
|
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, stream->num_in,
|
|
off, stream->num_ch_in, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pcm.num_in;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
|
|
off, stream->num_ch_out, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pcm.num_out;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
|
|
off, stream->num_ch_bd, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Create PDM DAIs */
|
|
stream = &cdns->pdm;
|
|
off += cdns->pcm.num_bd;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
|
|
off, stream->num_ch_in, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pdm.num_in;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
|
|
off, stream->num_ch_out, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pdm.num_bd;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
|
|
off, stream->num_ch_bd, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return snd_soc_register_component(cdns->dev, &dai_component,
|
|
dais, num_dai);
|
|
}
|
|
|
|
static int intel_prop_read(struct sdw_bus *bus)
|
|
{
|
|
/* Initialize with default handler to read all DisCo properties */
|
|
sdw_master_read_prop(bus);
|
|
|
|
/* BIOS is not giving some values correctly. So, lets override them */
|
|
bus->prop.num_clk_freq = 1;
|
|
bus->prop.clk_freq = devm_kcalloc(bus->dev, bus->prop.num_clk_freq,
|
|
sizeof(*bus->prop.clk_freq),
|
|
GFP_KERNEL);
|
|
if (!bus->prop.clk_freq)
|
|
return -ENOMEM;
|
|
|
|
bus->prop.clk_freq[0] = bus->prop.max_clk_freq;
|
|
bus->prop.err_threshold = 5;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct sdw_master_ops sdw_intel_ops = {
|
|
.read_prop = sdw_master_read_prop,
|
|
.xfer_msg = cdns_xfer_msg,
|
|
.xfer_msg_defer = cdns_xfer_msg_defer,
|
|
.reset_page_addr = cdns_reset_page_addr,
|
|
.set_bus_conf = cdns_bus_conf,
|
|
.pre_bank_switch = intel_pre_bank_switch,
|
|
.post_bank_switch = intel_post_bank_switch,
|
|
};
|
|
|
|
/*
|
|
* probe and init
|
|
*/
|
|
static int intel_probe(struct platform_device *pdev)
|
|
{
|
|
struct sdw_cdns_stream_config config;
|
|
struct sdw_intel *sdw;
|
|
int ret;
|
|
|
|
sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
|
|
if (!sdw)
|
|
return -ENOMEM;
|
|
|
|
sdw->instance = pdev->id;
|
|
sdw->res = dev_get_platdata(&pdev->dev);
|
|
sdw->cdns.dev = &pdev->dev;
|
|
sdw->cdns.registers = sdw->res->registers;
|
|
sdw->cdns.instance = sdw->instance;
|
|
sdw->cdns.msg_count = 0;
|
|
sdw->cdns.bus.dev = &pdev->dev;
|
|
sdw->cdns.bus.link_id = pdev->id;
|
|
|
|
sdw_cdns_probe(&sdw->cdns);
|
|
|
|
/* Set property read ops */
|
|
sdw_intel_ops.read_prop = intel_prop_read;
|
|
sdw->cdns.bus.ops = &sdw_intel_ops;
|
|
|
|
platform_set_drvdata(pdev, sdw);
|
|
|
|
ret = sdw_add_bus_master(&sdw->cdns.bus);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret);
|
|
goto err_master_reg;
|
|
}
|
|
|
|
/* Initialize shim and controller */
|
|
intel_link_power_up(sdw);
|
|
intel_shim_init(sdw);
|
|
|
|
ret = sdw_cdns_init(&sdw->cdns);
|
|
if (ret)
|
|
goto err_init;
|
|
|
|
ret = sdw_cdns_enable_interrupt(&sdw->cdns);
|
|
|
|
/* Read the PDI config and initialize cadence PDI */
|
|
intel_pdi_init(sdw, &config);
|
|
ret = sdw_cdns_pdi_init(&sdw->cdns, config);
|
|
if (ret)
|
|
goto err_init;
|
|
|
|
intel_pdi_ch_update(sdw);
|
|
|
|
/* Acquire IRQ */
|
|
ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread,
|
|
IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
|
|
if (ret < 0) {
|
|
dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
|
|
sdw->res->irq);
|
|
goto err_init;
|
|
}
|
|
|
|
/* Register DAIs */
|
|
ret = intel_register_dai(sdw);
|
|
if (ret) {
|
|
dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
|
|
snd_soc_unregister_component(sdw->cdns.dev);
|
|
goto err_dai;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_dai:
|
|
free_irq(sdw->res->irq, sdw);
|
|
err_init:
|
|
sdw_delete_bus_master(&sdw->cdns.bus);
|
|
err_master_reg:
|
|
return ret;
|
|
}
|
|
|
|
static int intel_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdw_intel *sdw;
|
|
|
|
sdw = platform_get_drvdata(pdev);
|
|
|
|
free_irq(sdw->res->irq, sdw);
|
|
snd_soc_unregister_component(sdw->cdns.dev);
|
|
sdw_delete_bus_master(&sdw->cdns.bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sdw_intel_drv = {
|
|
.probe = intel_probe,
|
|
.remove = intel_remove,
|
|
.driver = {
|
|
.name = "int-sdw",
|
|
|
|
},
|
|
};
|
|
|
|
module_platform_driver(sdw_intel_drv);
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
MODULE_ALIAS("platform:int-sdw");
|
|
MODULE_DESCRIPTION("Intel Soundwire Master Driver");
|