mirror of https://gitee.com/openkylin/linux.git
281 lines
7.3 KiB
C
281 lines
7.3 KiB
C
/*
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* cx18 System Control Block initialization
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@radix.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA
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*/
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#ifndef CX18_SCB_H
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#define CX18_SCB_H
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#include "cx18-mailbox.h"
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/* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
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are in the SW1 register. */
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#define IRQ_APU_TO_CPU 0x00000001
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#define IRQ_CPU_TO_APU_ACK 0x00000001
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#define IRQ_HPU_TO_CPU 0x00000002
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#define IRQ_CPU_TO_HPU_ACK 0x00000002
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#define IRQ_PPU_TO_CPU 0x00000004
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#define IRQ_CPU_TO_PPU_ACK 0x00000004
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#define IRQ_EPU_TO_CPU 0x00000008
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#define IRQ_CPU_TO_EPU_ACK 0x00000008
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#define IRQ_CPU_TO_APU 0x00000010
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#define IRQ_APU_TO_CPU_ACK 0x00000010
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#define IRQ_HPU_TO_APU 0x00000020
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#define IRQ_APU_TO_HPU_ACK 0x00000020
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#define IRQ_PPU_TO_APU 0x00000040
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#define IRQ_APU_TO_PPU_ACK 0x00000040
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#define IRQ_EPU_TO_APU 0x00000080
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#define IRQ_APU_TO_EPU_ACK 0x00000080
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#define IRQ_CPU_TO_HPU 0x00000100
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#define IRQ_HPU_TO_CPU_ACK 0x00000100
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#define IRQ_APU_TO_HPU 0x00000200
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#define IRQ_HPU_TO_APU_ACK 0x00000200
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#define IRQ_PPU_TO_HPU 0x00000400
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#define IRQ_HPU_TO_PPU_ACK 0x00000400
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#define IRQ_EPU_TO_HPU 0x00000800
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#define IRQ_HPU_TO_EPU_ACK 0x00000800
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#define IRQ_CPU_TO_PPU 0x00001000
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#define IRQ_PPU_TO_CPU_ACK 0x00001000
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#define IRQ_APU_TO_PPU 0x00002000
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#define IRQ_PPU_TO_APU_ACK 0x00002000
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#define IRQ_HPU_TO_PPU 0x00004000
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#define IRQ_PPU_TO_HPU_ACK 0x00004000
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#define IRQ_EPU_TO_PPU 0x00008000
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#define IRQ_PPU_TO_EPU_ACK 0x00008000
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#define IRQ_CPU_TO_EPU 0x00010000
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#define IRQ_EPU_TO_CPU_ACK 0x00010000
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#define IRQ_APU_TO_EPU 0x00020000
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#define IRQ_EPU_TO_APU_ACK 0x00020000
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#define IRQ_HPU_TO_EPU 0x00040000
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#define IRQ_EPU_TO_HPU_ACK 0x00040000
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#define IRQ_PPU_TO_EPU 0x00080000
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#define IRQ_EPU_TO_PPU_ACK 0x00080000
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#define SCB_OFFSET 0xDC0000
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/* If Firmware uses fixed memory map, it shall not allocate the area
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between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
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#define SCB_RESERVED_SIZE 0x10000
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/* This structure is used by EPU to provide memory descriptors in its memory */
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struct cx18_mdl {
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u32 paddr; /* Physical address of a buffer segment */
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u32 length; /* Length of the buffer segment */
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};
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struct cx18_scb {
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/* These fields form the System Control Block which is used at boot time
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for localizing the IPC data as well as the code positions for all
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processors. The offsets are from the start of this struct. */
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/* Offset where to find the Inter-Processor Communication data */
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u32 ipc_offset;
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u32 reserved01[7];
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/* Offset where to find the start of the CPU code */
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u32 cpu_code_offset;
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u32 reserved02[3];
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/* Offset where to find the start of the APU code */
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u32 apu_code_offset;
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u32 reserved03[3];
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/* Offset where to find the start of the HPU code */
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u32 hpu_code_offset;
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u32 reserved04[3];
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/* Offset where to find the start of the PPU code */
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u32 ppu_code_offset;
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u32 reserved05[3];
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/* These fields form Inter-Processor Communication data which is used
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by all processors to locate the information needed for communicating
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with other processors */
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/* Fields for CPU: */
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/* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
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u32 cpu_state;
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u32 reserved1[7];
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/* Offset to the mailbox used for sending commands from APU to CPU */
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u32 apu2cpu_mb_offset;
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/* Value to write to register SW1 register set (0xC7003100) after the
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command is ready */
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u32 apu2cpu_irq;
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/* Value to write to register SW2 register set (0xC7003140) after the
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command is cleared */
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u32 cpu2apu_irq_ack;
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u32 reserved2[13];
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u32 hpu2cpu_mb_offset;
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u32 hpu2cpu_irq;
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u32 cpu2hpu_irq_ack;
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u32 reserved3[13];
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u32 ppu2cpu_mb_offset;
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u32 ppu2cpu_irq;
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u32 cpu2ppu_irq_ack;
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u32 reserved4[13];
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u32 epu2cpu_mb_offset;
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u32 epu2cpu_irq;
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u32 cpu2epu_irq_ack;
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u32 reserved5[13];
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u32 reserved6[8];
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/* Fields for APU: */
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u32 apu_state;
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u32 reserved11[7];
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u32 cpu2apu_mb_offset;
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u32 cpu2apu_irq;
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u32 apu2cpu_irq_ack;
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u32 reserved12[13];
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u32 hpu2apu_mb_offset;
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u32 hpu2apu_irq;
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u32 apu2hpu_irq_ack;
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u32 reserved13[13];
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u32 ppu2apu_mb_offset;
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u32 ppu2apu_irq;
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u32 apu2ppu_irq_ack;
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u32 reserved14[13];
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u32 epu2apu_mb_offset;
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u32 epu2apu_irq;
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u32 apu2epu_irq_ack;
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u32 reserved15[13];
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u32 reserved16[8];
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/* Fields for HPU: */
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u32 hpu_state;
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u32 reserved21[7];
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u32 cpu2hpu_mb_offset;
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u32 cpu2hpu_irq;
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u32 hpu2cpu_irq_ack;
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u32 reserved22[13];
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u32 apu2hpu_mb_offset;
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u32 apu2hpu_irq;
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u32 hpu2apu_irq_ack;
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u32 reserved23[13];
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u32 ppu2hpu_mb_offset;
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u32 ppu2hpu_irq;
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u32 hpu2ppu_irq_ack;
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u32 reserved24[13];
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u32 epu2hpu_mb_offset;
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u32 epu2hpu_irq;
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u32 hpu2epu_irq_ack;
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u32 reserved25[13];
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u32 reserved26[8];
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/* Fields for PPU: */
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u32 ppu_state;
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u32 reserved31[7];
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u32 cpu2ppu_mb_offset;
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u32 cpu2ppu_irq;
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u32 ppu2cpu_irq_ack;
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u32 reserved32[13];
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u32 apu2ppu_mb_offset;
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u32 apu2ppu_irq;
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u32 ppu2apu_irq_ack;
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u32 reserved33[13];
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u32 hpu2ppu_mb_offset;
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u32 hpu2ppu_irq;
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u32 ppu2hpu_irq_ack;
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u32 reserved34[13];
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u32 epu2ppu_mb_offset;
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u32 epu2ppu_irq;
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u32 ppu2epu_irq_ack;
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u32 reserved35[13];
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u32 reserved36[8];
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/* Fields for EPU: */
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u32 epu_state;
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u32 reserved41[7];
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u32 cpu2epu_mb_offset;
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u32 cpu2epu_irq;
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u32 epu2cpu_irq_ack;
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u32 reserved42[13];
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u32 apu2epu_mb_offset;
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u32 apu2epu_irq;
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u32 epu2apu_irq_ack;
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u32 reserved43[13];
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u32 hpu2epu_mb_offset;
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u32 hpu2epu_irq;
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u32 epu2hpu_irq_ack;
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u32 reserved44[13];
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u32 ppu2epu_mb_offset;
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u32 ppu2epu_irq;
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u32 epu2ppu_irq_ack;
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u32 reserved45[13];
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u32 reserved46[8];
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u32 semaphores[8]; /* Semaphores */
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u32 reserved50[32]; /* Reserved for future use */
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struct cx18_mailbox apu2cpu_mb;
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struct cx18_mailbox hpu2cpu_mb;
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struct cx18_mailbox ppu2cpu_mb;
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struct cx18_mailbox epu2cpu_mb;
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struct cx18_mailbox cpu2apu_mb;
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struct cx18_mailbox hpu2apu_mb;
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struct cx18_mailbox ppu2apu_mb;
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struct cx18_mailbox epu2apu_mb;
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struct cx18_mailbox cpu2hpu_mb;
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struct cx18_mailbox apu2hpu_mb;
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struct cx18_mailbox ppu2hpu_mb;
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struct cx18_mailbox epu2hpu_mb;
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struct cx18_mailbox cpu2ppu_mb;
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struct cx18_mailbox apu2ppu_mb;
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struct cx18_mailbox hpu2ppu_mb;
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struct cx18_mailbox epu2ppu_mb;
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struct cx18_mailbox cpu2epu_mb;
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struct cx18_mailbox apu2epu_mb;
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struct cx18_mailbox hpu2epu_mb;
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struct cx18_mailbox ppu2epu_mb;
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struct cx18_mdl_ack cpu_mdl_ack[CX18_MAX_STREAMS][CX18_MAX_MDL_ACKS];
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struct cx18_mdl cpu_mdl[1];
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};
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void cx18_init_scb(struct cx18 *cx);
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#endif
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