mirror of https://gitee.com/openkylin/linux.git
173 lines
5.5 KiB
C
173 lines
5.5 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PGTABLE_HWDEF_H
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#define __ASM_PGTABLE_HWDEF_H
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#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
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/*
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* PMD_SHIFT determines the size a level 2 page table entry can map.
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*/
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#if CONFIG_PGTABLE_LEVELS > 2
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#define PMD_SHIFT ((PAGE_SHIFT - 3) * 2 + 3)
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#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PTRS_PER_PMD PTRS_PER_PTE
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#endif
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/*
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* PUD_SHIFT determines the size a level 1 page table entry can map.
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*/
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#if CONFIG_PGTABLE_LEVELS > 3
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#define PUD_SHIFT ((PAGE_SHIFT - 3) * 3 + 3)
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#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE-1))
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#define PTRS_PER_PUD PTRS_PER_PTE
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#endif
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/*
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* PGDIR_SHIFT determines the size a top-level page table entry can map
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* (depending on the configuration, this level can be 0, 1 or 2).
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*/
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#define PGDIR_SHIFT ((PAGE_SHIFT - 3) * CONFIG_PGTABLE_LEVELS + 3)
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#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
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/*
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* Section address mask and size definitions.
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*/
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#define SECTION_SHIFT PMD_SHIFT
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#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
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#define SECTION_MASK (~(SECTION_SIZE-1))
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/*
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* Hardware page table definitions.
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*
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* Level 1 descriptor (PUD).
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*/
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#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
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#define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1)
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#define PUD_TYPE_MASK (_AT(pgdval_t, 3) << 0)
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#define PUD_TYPE_SECT (_AT(pgdval_t, 1) << 0)
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/*
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* Level 2 descriptor (PMD).
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*/
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#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
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#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
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#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
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/*
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* Section
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*/
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#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
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#define PMD_SECT_PROT_NONE (_AT(pmdval_t, 1) << 58)
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#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
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#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
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#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
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#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
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#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
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#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
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#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
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#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
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/*
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* Level 3 descriptor (PTE).
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*/
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#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
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#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
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#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
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#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
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#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
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#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
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#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
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#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
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#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
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#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
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#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
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#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
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/*
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* 2nd stage PTE definitions
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*/
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#define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */
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#define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
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#define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */
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#define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
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/*
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* Memory Attribute override for Stage-2 (MemAttr[3:0])
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*/
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#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
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#define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2)
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/*
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* EL2/HYP PTE/PMD definitions
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*/
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#define PMD_HYP PMD_SECT_USER
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#define PTE_HYP PTE_USER
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/*
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* Highest possible physical address supported.
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*/
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#define PHYS_MASK_SHIFT (48)
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#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
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/*
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* TCR flags.
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*/
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#define TCR_T0SZ_OFFSET 0
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#define TCR_T1SZ_OFFSET 16
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#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
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#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
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#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))
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#define TCR_TxSZ_WIDTH 6
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#define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24))
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#define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24))
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#define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24))
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#define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24))
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#define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24))
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#define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26))
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#define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26))
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#define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26))
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#define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26))
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#define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26))
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#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))
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#define TCR_TG0_4K (UL(0) << 14)
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#define TCR_TG0_64K (UL(1) << 14)
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#define TCR_TG0_16K (UL(2) << 14)
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#define TCR_TG1_16K (UL(1) << 30)
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#define TCR_TG1_4K (UL(2) << 30)
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#define TCR_TG1_64K (UL(3) << 30)
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#define TCR_ASID16 (UL(1) << 36)
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#define TCR_TBI0 (UL(1) << 37)
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#endif
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