mirror of https://gitee.com/openkylin/linux.git
697 lines
18 KiB
C
697 lines
18 KiB
C
/*
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* Performance event support for s390x - CPU-measurement Counter Facility
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*
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* Copyright IBM Corp. 2012
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* Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License (version 2 only)
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* as published by the Free Software Foundation.
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*/
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#define KMSG_COMPONENT "cpum_cf"
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#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
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#include <linux/kernel.h>
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#include <linux/kernel_stat.h>
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#include <linux/perf_event.h>
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#include <linux/percpu.h>
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#include <linux/notifier.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <asm/ctl_reg.h>
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#include <asm/irq.h>
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#include <asm/cpu_mf.h>
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/* CPU-measurement counter facility supports these CPU counter sets:
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* For CPU counter sets:
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* Basic counter set: 0-31
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* Problem-state counter set: 32-63
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* Crypto-activity counter set: 64-127
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* Extented counter set: 128-159
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*/
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enum cpumf_ctr_set {
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/* CPU counter sets */
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CPUMF_CTR_SET_BASIC = 0,
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CPUMF_CTR_SET_USER = 1,
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CPUMF_CTR_SET_CRYPTO = 2,
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CPUMF_CTR_SET_EXT = 3,
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/* Maximum number of counter sets */
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CPUMF_CTR_SET_MAX,
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};
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#define CPUMF_LCCTL_ENABLE_SHIFT 16
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#define CPUMF_LCCTL_ACTCTL_SHIFT 0
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static const u64 cpumf_state_ctl[CPUMF_CTR_SET_MAX] = {
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[CPUMF_CTR_SET_BASIC] = 0x02,
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[CPUMF_CTR_SET_USER] = 0x04,
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[CPUMF_CTR_SET_CRYPTO] = 0x08,
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[CPUMF_CTR_SET_EXT] = 0x01,
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};
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static void ctr_set_enable(u64 *state, int ctr_set)
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{
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*state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT;
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}
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static void ctr_set_disable(u64 *state, int ctr_set)
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{
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*state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT);
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}
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static void ctr_set_start(u64 *state, int ctr_set)
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{
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*state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT;
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}
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static void ctr_set_stop(u64 *state, int ctr_set)
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{
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*state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT);
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}
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/* Local CPUMF event structure */
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struct cpu_hw_events {
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struct cpumf_ctr_info info;
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atomic_t ctr_set[CPUMF_CTR_SET_MAX];
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u64 state, tx_state;
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unsigned int flags;
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};
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static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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.ctr_set = {
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[CPUMF_CTR_SET_BASIC] = ATOMIC_INIT(0),
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[CPUMF_CTR_SET_USER] = ATOMIC_INIT(0),
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[CPUMF_CTR_SET_CRYPTO] = ATOMIC_INIT(0),
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[CPUMF_CTR_SET_EXT] = ATOMIC_INIT(0),
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},
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.state = 0,
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.flags = 0,
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};
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static int get_counter_set(u64 event)
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{
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int set = -1;
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if (event < 32)
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set = CPUMF_CTR_SET_BASIC;
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else if (event < 64)
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set = CPUMF_CTR_SET_USER;
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else if (event < 128)
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set = CPUMF_CTR_SET_CRYPTO;
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else if (event < 256)
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set = CPUMF_CTR_SET_EXT;
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return set;
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}
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static int validate_event(const struct hw_perf_event *hwc)
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{
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switch (hwc->config_base) {
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case CPUMF_CTR_SET_BASIC:
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case CPUMF_CTR_SET_USER:
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case CPUMF_CTR_SET_CRYPTO:
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case CPUMF_CTR_SET_EXT:
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/* check for reserved counters */
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if ((hwc->config >= 6 && hwc->config <= 31) ||
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(hwc->config >= 38 && hwc->config <= 63) ||
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(hwc->config >= 80 && hwc->config <= 127))
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return -EOPNOTSUPP;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int validate_ctr_version(const struct hw_perf_event *hwc)
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{
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struct cpu_hw_events *cpuhw;
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int err = 0;
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cpuhw = &get_cpu_var(cpu_hw_events);
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/* check required version for counter sets */
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switch (hwc->config_base) {
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case CPUMF_CTR_SET_BASIC:
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case CPUMF_CTR_SET_USER:
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if (cpuhw->info.cfvn < 1)
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err = -EOPNOTSUPP;
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break;
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case CPUMF_CTR_SET_CRYPTO:
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case CPUMF_CTR_SET_EXT:
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if (cpuhw->info.csvn < 1)
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err = -EOPNOTSUPP;
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if ((cpuhw->info.csvn == 1 && hwc->config > 159) ||
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(cpuhw->info.csvn == 2 && hwc->config > 175) ||
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(cpuhw->info.csvn > 2 && hwc->config > 255))
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err = -EOPNOTSUPP;
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break;
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}
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put_cpu_var(cpu_hw_events);
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return err;
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}
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static int validate_ctr_auth(const struct hw_perf_event *hwc)
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{
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struct cpu_hw_events *cpuhw;
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u64 ctrs_state;
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int err = 0;
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cpuhw = &get_cpu_var(cpu_hw_events);
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/* check authorization for cpu counter sets */
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ctrs_state = cpumf_state_ctl[hwc->config_base];
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if (!(ctrs_state & cpuhw->info.auth_ctl))
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err = -EPERM;
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put_cpu_var(cpu_hw_events);
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return err;
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}
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/*
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* Change the CPUMF state to active.
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* Enable and activate the CPU-counter sets according
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* to the per-cpu control state.
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*/
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static void cpumf_pmu_enable(struct pmu *pmu)
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{
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struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
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int err;
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if (cpuhw->flags & PMU_F_ENABLED)
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return;
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err = lcctl(cpuhw->state);
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if (err) {
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pr_err("Enabling the performance measuring unit "
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"failed with rc=%x\n", err);
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return;
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}
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cpuhw->flags |= PMU_F_ENABLED;
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}
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/*
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* Change the CPUMF state to inactive.
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* Disable and enable (inactive) the CPU-counter sets according
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* to the per-cpu control state.
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*/
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static void cpumf_pmu_disable(struct pmu *pmu)
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{
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struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
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int err;
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u64 inactive;
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if (!(cpuhw->flags & PMU_F_ENABLED))
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return;
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inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1);
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err = lcctl(inactive);
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if (err) {
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pr_err("Disabling the performance measuring unit "
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"failed with rc=%x\n", err);
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return;
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}
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cpuhw->flags &= ~PMU_F_ENABLED;
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}
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/* Number of perf events counting hardware events */
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static atomic_t num_events = ATOMIC_INIT(0);
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/* Used to avoid races in calling reserve/release_cpumf_hardware */
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static DEFINE_MUTEX(pmc_reserve_mutex);
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/* CPU-measurement alerts for the counter facility */
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static void cpumf_measurement_alert(struct ext_code ext_code,
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unsigned int alert, unsigned long unused)
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{
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struct cpu_hw_events *cpuhw;
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if (!(alert & CPU_MF_INT_CF_MASK))
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return;
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inc_irq_stat(IRQEXT_CMC);
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cpuhw = this_cpu_ptr(&cpu_hw_events);
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/* Measurement alerts are shared and might happen when the PMU
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* is not reserved. Ignore these alerts in this case. */
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if (!(cpuhw->flags & PMU_F_RESERVED))
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return;
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/* counter authorization change alert */
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if (alert & CPU_MF_INT_CF_CACA)
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qctri(&cpuhw->info);
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/* loss of counter data alert */
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if (alert & CPU_MF_INT_CF_LCDA)
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pr_err("CPU[%i] Counter data was lost\n", smp_processor_id());
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}
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#define PMC_INIT 0
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#define PMC_RELEASE 1
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static void setup_pmc_cpu(void *flags)
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{
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struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
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switch (*((int *) flags)) {
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case PMC_INIT:
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memset(&cpuhw->info, 0, sizeof(cpuhw->info));
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qctri(&cpuhw->info);
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cpuhw->flags |= PMU_F_RESERVED;
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break;
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case PMC_RELEASE:
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cpuhw->flags &= ~PMU_F_RESERVED;
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break;
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}
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/* Disable CPU counter sets */
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lcctl(0);
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}
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/* Initialize the CPU-measurement facility */
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static int reserve_pmc_hardware(void)
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{
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int flags = PMC_INIT;
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on_each_cpu(setup_pmc_cpu, &flags, 1);
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irq_subclass_register(IRQ_SUBCLASS_MEASUREMENT_ALERT);
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return 0;
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}
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/* Release the CPU-measurement facility */
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static void release_pmc_hardware(void)
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{
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int flags = PMC_RELEASE;
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on_each_cpu(setup_pmc_cpu, &flags, 1);
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irq_subclass_unregister(IRQ_SUBCLASS_MEASUREMENT_ALERT);
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}
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/* Release the PMU if event is the last perf event */
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static void hw_perf_event_destroy(struct perf_event *event)
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{
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if (!atomic_add_unless(&num_events, -1, 1)) {
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mutex_lock(&pmc_reserve_mutex);
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if (atomic_dec_return(&num_events) == 0)
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release_pmc_hardware();
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mutex_unlock(&pmc_reserve_mutex);
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}
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}
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/* CPUMF <-> perf event mappings for kernel+userspace (basic set) */
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static const int cpumf_generic_events_basic[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = 0,
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[PERF_COUNT_HW_INSTRUCTIONS] = 1,
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[PERF_COUNT_HW_CACHE_REFERENCES] = -1,
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[PERF_COUNT_HW_CACHE_MISSES] = -1,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
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[PERF_COUNT_HW_BRANCH_MISSES] = -1,
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[PERF_COUNT_HW_BUS_CYCLES] = -1,
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};
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/* CPUMF <-> perf event mappings for userspace (problem-state set) */
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static const int cpumf_generic_events_user[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = 32,
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[PERF_COUNT_HW_INSTRUCTIONS] = 33,
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[PERF_COUNT_HW_CACHE_REFERENCES] = -1,
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[PERF_COUNT_HW_CACHE_MISSES] = -1,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
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[PERF_COUNT_HW_BRANCH_MISSES] = -1,
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[PERF_COUNT_HW_BUS_CYCLES] = -1,
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};
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static int __hw_perf_event_init(struct perf_event *event)
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{
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struct perf_event_attr *attr = &event->attr;
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struct hw_perf_event *hwc = &event->hw;
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int err;
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u64 ev;
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switch (attr->type) {
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case PERF_TYPE_RAW:
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/* Raw events are used to access counters directly,
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* hence do not permit excludes */
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if (attr->exclude_kernel || attr->exclude_user ||
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attr->exclude_hv)
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return -EOPNOTSUPP;
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ev = attr->config;
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break;
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case PERF_TYPE_HARDWARE:
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ev = attr->config;
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/* Count user space (problem-state) only */
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if (!attr->exclude_user && attr->exclude_kernel) {
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if (ev >= ARRAY_SIZE(cpumf_generic_events_user))
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return -EOPNOTSUPP;
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ev = cpumf_generic_events_user[ev];
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/* No support for kernel space counters only */
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} else if (!attr->exclude_kernel && attr->exclude_user) {
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return -EOPNOTSUPP;
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/* Count user and kernel space */
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} else {
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if (ev >= ARRAY_SIZE(cpumf_generic_events_basic))
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return -EOPNOTSUPP;
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ev = cpumf_generic_events_basic[ev];
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}
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break;
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default:
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return -ENOENT;
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}
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if (ev == -1)
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return -ENOENT;
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if (ev >= PERF_CPUM_CF_MAX_CTR)
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return -EINVAL;
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/* Use the hardware perf event structure to store the counter number
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* in 'config' member and the counter set to which the counter belongs
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* in the 'config_base'. The counter set (config_base) is then used
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* to enable/disable the counters.
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*/
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hwc->config = ev;
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hwc->config_base = get_counter_set(ev);
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/* Validate the counter that is assigned to this event.
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* Because the counter facility can use numerous counters at the
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* same time without constraints, it is not necessary to explicity
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* validate event groups (event->group_leader != event).
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*/
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err = validate_event(hwc);
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if (err)
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return err;
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/* Initialize for using the CPU-measurement counter facility */
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if (!atomic_inc_not_zero(&num_events)) {
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mutex_lock(&pmc_reserve_mutex);
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if (atomic_read(&num_events) == 0 && reserve_pmc_hardware())
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err = -EBUSY;
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else
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atomic_inc(&num_events);
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mutex_unlock(&pmc_reserve_mutex);
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}
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event->destroy = hw_perf_event_destroy;
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/* Finally, validate version and authorization of the counter set */
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err = validate_ctr_auth(hwc);
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if (!err)
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err = validate_ctr_version(hwc);
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return err;
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}
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static int cpumf_pmu_event_init(struct perf_event *event)
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{
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int err;
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switch (event->attr.type) {
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case PERF_TYPE_HARDWARE:
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case PERF_TYPE_HW_CACHE:
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case PERF_TYPE_RAW:
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err = __hw_perf_event_init(event);
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break;
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default:
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return -ENOENT;
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}
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if (unlikely(err) && event->destroy)
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event->destroy(event);
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return err;
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}
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static int hw_perf_event_reset(struct perf_event *event)
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{
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u64 prev, new;
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int err;
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do {
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prev = local64_read(&event->hw.prev_count);
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err = ecctr(event->hw.config, &new);
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if (err) {
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if (err != 3)
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break;
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/* The counter is not (yet) available. This
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* might happen if the counter set to which
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* this counter belongs is in the disabled
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* state.
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*/
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new = 0;
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}
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} while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
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return err;
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}
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static int hw_perf_event_update(struct perf_event *event)
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{
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u64 prev, new, delta;
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int err;
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do {
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prev = local64_read(&event->hw.prev_count);
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err = ecctr(event->hw.config, &new);
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if (err)
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goto out;
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} while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev);
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delta = (prev <= new) ? new - prev
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: (-1ULL - prev) + new + 1; /* overflow */
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local64_add(delta, &event->count);
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out:
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return err;
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}
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static void cpumf_pmu_read(struct perf_event *event)
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{
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if (event->hw.state & PERF_HES_STOPPED)
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return;
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hw_perf_event_update(event);
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}
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static void cpumf_pmu_start(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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return;
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if (WARN_ON_ONCE(hwc->config == -1))
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return;
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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/* (Re-)enable and activate the counter set */
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ctr_set_enable(&cpuhw->state, hwc->config_base);
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ctr_set_start(&cpuhw->state, hwc->config_base);
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/* The counter set to which this counter belongs can be already active.
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* Because all counters in a set are active, the event->hw.prev_count
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* needs to be synchronized. At this point, the counter set can be in
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* the inactive or disabled state.
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*/
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hw_perf_event_reset(event);
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/* increment refcount for this counter set */
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atomic_inc(&cpuhw->ctr_set[hwc->config_base]);
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}
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static void cpumf_pmu_stop(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
if (!(hwc->state & PERF_HES_STOPPED)) {
|
|
/* Decrement reference count for this counter set and if this
|
|
* is the last used counter in the set, clear activation
|
|
* control and set the counter set state to inactive.
|
|
*/
|
|
if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base]))
|
|
ctr_set_stop(&cpuhw->state, hwc->config_base);
|
|
event->hw.state |= PERF_HES_STOPPED;
|
|
}
|
|
|
|
if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
|
|
hw_perf_event_update(event);
|
|
event->hw.state |= PERF_HES_UPTODATE;
|
|
}
|
|
}
|
|
|
|
static int cpumf_pmu_add(struct perf_event *event, int flags)
|
|
{
|
|
struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
|
|
|
|
/* Check authorization for the counter set to which this
|
|
* counter belongs.
|
|
* For group events transaction, the authorization check is
|
|
* done in cpumf_pmu_commit_txn().
|
|
*/
|
|
if (!(cpuhw->flags & PERF_EVENT_TXN))
|
|
if (validate_ctr_auth(&event->hw))
|
|
return -EPERM;
|
|
|
|
ctr_set_enable(&cpuhw->state, event->hw.config_base);
|
|
event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
|
|
|
|
if (flags & PERF_EF_START)
|
|
cpumf_pmu_start(event, PERF_EF_RELOAD);
|
|
|
|
perf_event_update_userpage(event);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cpumf_pmu_del(struct perf_event *event, int flags)
|
|
{
|
|
struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
|
|
|
|
cpumf_pmu_stop(event, PERF_EF_UPDATE);
|
|
|
|
/* Check if any counter in the counter set is still used. If not used,
|
|
* change the counter set to the disabled state. This also clears the
|
|
* content of all counters in the set.
|
|
*
|
|
* When a new perf event has been added but not yet started, this can
|
|
* clear enable control and resets all counters in a set. Therefore,
|
|
* cpumf_pmu_start() always has to reenable a counter set.
|
|
*/
|
|
if (!atomic_read(&cpuhw->ctr_set[event->hw.config_base]))
|
|
ctr_set_disable(&cpuhw->state, event->hw.config_base);
|
|
|
|
perf_event_update_userpage(event);
|
|
}
|
|
|
|
/*
|
|
* Start group events scheduling transaction.
|
|
* Set flags to perform a single test at commit time.
|
|
*/
|
|
static void cpumf_pmu_start_txn(struct pmu *pmu)
|
|
{
|
|
struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
|
|
|
|
perf_pmu_disable(pmu);
|
|
cpuhw->flags |= PERF_EVENT_TXN;
|
|
cpuhw->tx_state = cpuhw->state;
|
|
}
|
|
|
|
/*
|
|
* Stop and cancel a group events scheduling tranctions.
|
|
* Assumes cpumf_pmu_del() is called for each successful added
|
|
* cpumf_pmu_add() during the transaction.
|
|
*/
|
|
static void cpumf_pmu_cancel_txn(struct pmu *pmu)
|
|
{
|
|
struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
|
|
|
|
WARN_ON(cpuhw->tx_state != cpuhw->state);
|
|
|
|
cpuhw->flags &= ~PERF_EVENT_TXN;
|
|
perf_pmu_enable(pmu);
|
|
}
|
|
|
|
/*
|
|
* Commit the group events scheduling transaction. On success, the
|
|
* transaction is closed. On error, the transaction is kept open
|
|
* until cpumf_pmu_cancel_txn() is called.
|
|
*/
|
|
static int cpumf_pmu_commit_txn(struct pmu *pmu)
|
|
{
|
|
struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
|
|
u64 state;
|
|
|
|
/* check if the updated state can be scheduled */
|
|
state = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1);
|
|
state >>= CPUMF_LCCTL_ENABLE_SHIFT;
|
|
if ((state & cpuhw->info.auth_ctl) != state)
|
|
return -EPERM;
|
|
|
|
cpuhw->flags &= ~PERF_EVENT_TXN;
|
|
perf_pmu_enable(pmu);
|
|
return 0;
|
|
}
|
|
|
|
/* Performance monitoring unit for s390x */
|
|
static struct pmu cpumf_pmu = {
|
|
.pmu_enable = cpumf_pmu_enable,
|
|
.pmu_disable = cpumf_pmu_disable,
|
|
.event_init = cpumf_pmu_event_init,
|
|
.add = cpumf_pmu_add,
|
|
.del = cpumf_pmu_del,
|
|
.start = cpumf_pmu_start,
|
|
.stop = cpumf_pmu_stop,
|
|
.read = cpumf_pmu_read,
|
|
.start_txn = cpumf_pmu_start_txn,
|
|
.commit_txn = cpumf_pmu_commit_txn,
|
|
.cancel_txn = cpumf_pmu_cancel_txn,
|
|
};
|
|
|
|
static int cpumf_pmu_notifier(struct notifier_block *self, unsigned long action,
|
|
void *hcpu)
|
|
{
|
|
unsigned int cpu = (long) hcpu;
|
|
int flags;
|
|
|
|
switch (action & ~CPU_TASKS_FROZEN) {
|
|
case CPU_ONLINE:
|
|
flags = PMC_INIT;
|
|
smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1);
|
|
break;
|
|
case CPU_DOWN_PREPARE:
|
|
flags = PMC_RELEASE;
|
|
smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static int __init cpumf_pmu_init(void)
|
|
{
|
|
int rc;
|
|
|
|
if (!cpum_cf_avail())
|
|
return -ENODEV;
|
|
|
|
/* clear bit 15 of cr0 to unauthorize problem-state to
|
|
* extract measurement counters */
|
|
ctl_clear_bit(0, 48);
|
|
|
|
/* register handler for measurement-alert interruptions */
|
|
rc = register_external_irq(EXT_IRQ_MEASURE_ALERT,
|
|
cpumf_measurement_alert);
|
|
if (rc) {
|
|
pr_err("Registering for CPU-measurement alerts "
|
|
"failed with rc=%i\n", rc);
|
|
goto out;
|
|
}
|
|
|
|
/* The CPU measurement counter facility does not have overflow
|
|
* interrupts to do sampling. Sampling must be provided by
|
|
* external means, for example, by timers.
|
|
*/
|
|
cpumf_pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
|
|
|
|
cpumf_pmu.attr_groups = cpumf_cf_event_group();
|
|
rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW);
|
|
if (rc) {
|
|
pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc);
|
|
unregister_external_irq(EXT_IRQ_MEASURE_ALERT,
|
|
cpumf_measurement_alert);
|
|
goto out;
|
|
}
|
|
perf_cpu_notifier(cpumf_pmu_notifier);
|
|
out:
|
|
return rc;
|
|
}
|
|
early_initcall(cpumf_pmu_init);
|