mirror of https://gitee.com/openkylin/linux.git
229 lines
4.9 KiB
Plaintext
229 lines
4.9 KiB
Plaintext
/*
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* Copyright 2016 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include "arm-realview-pbx.dtsi"
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/ {
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/*
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* This is the RealView Platform Baseboard Explore for Cortex-A9
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* (HBI0182 + HBI0183) as described in ARM DUI 0440B
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*/
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model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
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arm,hbi = <0x182>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "arm,realview-smp";
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x1>;
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next-level-cache = <&L2>;
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};
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x1f002000 0x1000>;
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cache-unified;
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cache-level = <2>;
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/*
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* Override default cache size, sets and
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* associativity as these may be erroneously set
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* up by boot loader(s).
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*/
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cache-size = <131072>; // 128KB
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cache-sets = <512>;
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cache-line-size = <32>;
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arm,parity-disable;
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arm,tag-latency = <1 1 1>;
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arm,data-latency = <1 1 1>;
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};
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scu: scu@1f000000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1f000000 0x100>;
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};
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twd_timer: timer@1f000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1f000600 0x20>;
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interrupt-parent = <&intc>;
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interrupts = <1 13 0xf04>;
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};
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twd_wdog: watchdog@1f000620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x1f000620 0x20>;
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interrupt-parent = <&intc>;
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interrupts = <1 14 0xf04>;
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};
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pmu: pmu@0 {
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&intc>;
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interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
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<0 45 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&CPU0>, <&CPU1>;
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};
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/* Primary GIC PL390 interrupt controller in the test chip */
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intc: interrupt-controller@1f000000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x1f001000 0x1000>,
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<0x1f000100 0x100>;
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};
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};
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ðernet {
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interrupt-parent = <&intc>;
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interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usb {
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interrupt-parent = <&intc>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial0 {
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interrupt-parent = <&intc>;
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interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial1 {
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interrupt-parent = <&intc>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial2 {
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interrupt-parent = <&intc>;
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interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
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};
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&serial3 {
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interrupt-parent = <&intc>;
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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&ssp {
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interrupt-parent = <&intc>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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};
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&wdog0 {
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interrupt-parent = <&intc>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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&wdog1 {
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interrupt-parent = <&intc>;
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interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer01 {
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interrupt-parent = <&intc>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer23 {
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interrupt-parent = <&intc>;
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio0 {
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interrupt-parent = <&intc>;
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interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio1 {
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interrupt-parent = <&intc>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio2 {
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interrupt-parent = <&intc>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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&rtc {
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interrupt-parent = <&intc>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer45 {
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interrupt-parent = <&intc>;
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interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
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};
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&timer67 {
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interrupt-parent = <&intc>;
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interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
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};
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&aaci {
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interrupt-parent = <&intc>;
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interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
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};
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&mmc {
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interrupt-parent = <&intc>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 18 IRQ_TYPE_LEVEL_HIGH>;
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};
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&kmi0 {
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interrupt-parent = <&intc>;
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interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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&kmi1 {
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interrupt-parent = <&intc>;
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interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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&clcd {
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interrupt-parent = <&intc>;
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interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
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};
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