mirror of https://gitee.com/openkylin/linux.git
506 lines
14 KiB
C
506 lines
14 KiB
C
/* ASB2305 PCI support
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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* Derived from arch/i386/kernel/pci-pc.c
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* (c) 1999--2000 Martin Mares <mj@suse.cz>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include "pci-asb2305.h"
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unsigned int pci_probe = 1;
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struct pci_ops *pci_root_ops;
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/*
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* The accessible PCI window does not cover the entire CPU address space, but
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* there are devices we want to access outside of that window, so we need to
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* insert specific PCI bus resources instead of using the platform-level bus
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* resources directly for the PCI root bus.
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*
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* These are configured and inserted by pcibios_init().
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*/
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static struct resource pci_ioport_resource = {
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.name = "PCI IO",
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.start = 0xbe000000,
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.end = 0xbe03ffff,
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.flags = IORESOURCE_IO,
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};
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static struct resource pci_iomem_resource = {
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.name = "PCI mem",
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.start = 0xb8000000,
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.end = 0xbbffffff,
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.flags = IORESOURCE_MEM,
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};
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/*
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* Functions for accessing PCI configuration space
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*/
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#define CONFIG_CMD(bus, devfn, where) \
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(0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
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#define MEM_PAGING_REG (*(volatile __u32 *) 0xBFFFFFF4)
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#define CONFIG_ADDRESS (*(volatile __u32 *) 0xBFFFFFF8)
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#define CONFIG_DATAL(X) (*(volatile __u32 *) 0xBFFFFFFC)
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#define CONFIG_DATAW(X) (*(volatile __u16 *) (0xBFFFFFFC + ((X) & 2)))
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#define CONFIG_DATAB(X) (*(volatile __u8 *) (0xBFFFFFFC + ((X) & 3)))
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#define BRIDGEREGB(X) (*(volatile __u8 *) (0xBE040000 + (X)))
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#define BRIDGEREGW(X) (*(volatile __u16 *) (0xBE040000 + (X)))
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#define BRIDGEREGL(X) (*(volatile __u32 *) (0xBE040000 + (X)))
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static inline int __query(const struct pci_bus *bus, unsigned int devfn)
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{
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#if 0
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return bus->number == 0 && (devfn == PCI_DEVFN(0, 0));
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return bus->number == 1;
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return bus->number == 0 &&
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(devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0));
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#endif
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return 1;
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}
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/*
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*
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*/
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static int pci_ampci_read_config_byte(struct pci_bus *bus, unsigned int devfn,
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int where, u32 *_value)
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{
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u32 rawval, value;
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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value = BRIDGEREGB(where);
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__pcbdebug("=> %02hx", &BRIDGEREGL(where), value);
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} else {
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CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
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rawval = CONFIG_ADDRESS;
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value = CONFIG_DATAB(where);
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if (__query(bus, devfn))
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__pcidebug("=> %02hx", bus, devfn, where, value);
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}
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*_value = value;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_ampci_read_config_word(struct pci_bus *bus, unsigned int devfn,
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int where, u32 *_value)
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{
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u32 rawval, value;
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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value = BRIDGEREGW(where);
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__pcbdebug("=> %04hx", &BRIDGEREGL(where), value);
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} else {
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CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
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rawval = CONFIG_ADDRESS;
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value = CONFIG_DATAW(where);
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if (__query(bus, devfn))
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__pcidebug("=> %04hx", bus, devfn, where, value);
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}
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*_value = value;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_ampci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, u32 *_value)
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{
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u32 rawval, value;
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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value = BRIDGEREGL(where);
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__pcbdebug("=> %08x", &BRIDGEREGL(where), value);
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} else {
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CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
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rawval = CONFIG_ADDRESS;
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value = CONFIG_DATAL(where);
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if (__query(bus, devfn))
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__pcidebug("=> %08x", bus, devfn, where, value);
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}
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*_value = value;
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_ampci_write_config_byte(struct pci_bus *bus, unsigned int devfn,
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int where, u8 value)
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{
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u32 rawval;
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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__pcbdebug("<= %02x", &BRIDGEREGB(where), value);
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BRIDGEREGB(where) = value;
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} else {
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if (bus->number == 0 &&
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(devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0))
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)
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__pcidebug("<= %02x", bus, devfn, where, value);
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CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
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rawval = CONFIG_ADDRESS;
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CONFIG_DATAB(where) = value;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_ampci_write_config_word(struct pci_bus *bus, unsigned int devfn,
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int where, u16 value)
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{
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u32 rawval;
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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__pcbdebug("<= %04hx", &BRIDGEREGW(where), value);
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BRIDGEREGW(where) = value;
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} else {
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if (__query(bus, devfn))
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__pcidebug("<= %04hx", bus, devfn, where, value);
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CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
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rawval = CONFIG_ADDRESS;
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CONFIG_DATAW(where) = value;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_ampci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, u32 value)
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{
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u32 rawval;
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if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
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__pcbdebug("<= %08x", &BRIDGEREGL(where), value);
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BRIDGEREGL(where) = value;
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} else {
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if (__query(bus, devfn))
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__pcidebug("<= %08x", bus, devfn, where, value);
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CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
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rawval = CONFIG_ADDRESS;
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CONFIG_DATAL(where) = value;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_ampci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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switch (size) {
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case 1:
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return pci_ampci_read_config_byte(bus, devfn, where, val);
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case 2:
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return pci_ampci_read_config_word(bus, devfn, where, val);
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case 4:
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return pci_ampci_read_config_dword(bus, devfn, where, val);
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default:
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BUG();
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return -EOPNOTSUPP;
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}
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}
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static int pci_ampci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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switch (size) {
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case 1:
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return pci_ampci_write_config_byte(bus, devfn, where, val);
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case 2:
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return pci_ampci_write_config_word(bus, devfn, where, val);
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case 4:
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return pci_ampci_write_config_dword(bus, devfn, where, val);
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default:
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BUG();
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return -EOPNOTSUPP;
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}
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}
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static struct pci_ops pci_direct_ampci = {
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.read = pci_ampci_read_config,
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.write = pci_ampci_write_config,
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};
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/*
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* Before we decide to use direct hardware access mechanisms, we try to do some
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* trivial checks to ensure it at least _seems_ to be working -- we just test
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* whether bus 00 contains a host bridge (this is similar to checking
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* techniques used in XFree86, but ours should be more reliable since we
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* attempt to make use of direct access hints provided by the PCI BIOS).
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*
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* This should be close to trivial, but it isn't, because there are buggy
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* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
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*/
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static int __init pci_sanity_check(struct pci_ops *o)
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{
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struct pci_bus bus; /* Fake bus and device */
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u32 x;
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bus.number = 0;
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if ((!o->read(&bus, 0, PCI_CLASS_DEVICE, 2, &x) &&
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(x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
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(!o->read(&bus, 0, PCI_VENDOR_ID, 2, &x) &&
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(x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
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return 1;
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printk(KERN_ERR "PCI: Sanity check failed\n");
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return 0;
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}
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static int __init pci_check_direct(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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/*
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* Check if access works.
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*/
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if (pci_sanity_check(&pci_direct_ampci)) {
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local_irq_restore(flags);
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printk(KERN_INFO "PCI: Using configuration ampci\n");
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request_mem_region(0xBE040000, 256, "AMPCI bridge");
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request_mem_region(0xBFFFFFF4, 12, "PCI ampci");
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request_mem_region(0xBC000000, 32 * 1024 * 1024, "PCI SRAM");
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return 0;
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}
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local_irq_restore(flags);
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return -ENODEV;
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}
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static void pcibios_fixup_device_resources(struct pci_dev *dev)
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{
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int idx;
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if (!dev->bus)
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return;
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for (idx = 0; idx < PCI_BRIDGE_RESOURCES; idx++) {
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struct resource *r = &dev->resource[idx];
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if (!r->flags || r->parent || !r->start)
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continue;
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pci_claim_resource(dev, idx);
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}
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}
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static void pcibios_fixup_bridge_resources(struct pci_dev *dev)
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{
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int idx;
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if (!dev->bus)
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return;
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for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
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struct resource *r = &dev->resource[idx];
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if (!r->flags || r->parent || !r->start)
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continue;
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pci_claim_bridge_resource(dev, idx);
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}
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}
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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if (bus->self) {
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pci_read_bridge_bases(bus);
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pcibios_fixup_bridge_resources(bus->self);
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}
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list_for_each_entry(dev, &bus->devices, bus_list)
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pcibios_fixup_device_resources(dev);
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}
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/*
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* Initialization. Try all known PCI access methods. Note that we support
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* using both PCI BIOS and direct access: in such cases, we use I/O ports
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* to access config space, but we still keep BIOS order of cards to be
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* compatible with 2.0.X. This should go away some day.
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*/
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static int __init pcibios_init(void)
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{
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resource_size_t io_offset, mem_offset;
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LIST_HEAD(resources);
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struct pci_bus *bus;
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ioport_resource.start = 0xA0000000;
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ioport_resource.end = 0xDFFFFFFF;
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iomem_resource.start = 0xA0000000;
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iomem_resource.end = 0xDFFFFFFF;
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if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
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panic("Unable to insert PCI IOMEM resource\n");
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if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
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panic("Unable to insert PCI IOPORT resource\n");
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if (!pci_probe)
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return 0;
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if (pci_check_direct() < 0) {
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printk(KERN_WARNING "PCI: No PCI bus detected\n");
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return 0;
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}
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printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
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MEM_PAGING_REG);
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io_offset = pci_ioport_resource.start -
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(pci_ioport_resource.start & 0x00ffffff);
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mem_offset = pci_iomem_resource.start -
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((pci_iomem_resource.start & 0x03ffffff) | MEM_PAGING_REG);
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pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset);
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pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset);
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bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, &resources);
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if (!bus)
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return 0;
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pcibios_irq_init();
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pcibios_fixup_irqs();
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pcibios_resource_survey();
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pci_bus_add_devices(bus);
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return 0;
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}
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arch_initcall(pcibios_init);
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char *__init pcibios_setup(char *str)
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{
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if (!strcmp(str, "off")) {
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pci_probe = 0;
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return NULL;
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}
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return str;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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int err;
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err = pci_enable_resources(dev, mask);
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if (err == 0)
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pcibios_enable_irq(dev);
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return err;
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}
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/*
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* disable the ethernet chipset
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*/
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static void __init unit_disable_pcnet(struct pci_bus *bus, struct pci_ops *o)
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{
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u32 x;
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bus->number = 0;
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o->read (bus, PCI_DEVFN(2, 0), PCI_VENDOR_ID, 4, &x);
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o->read (bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, &x);
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x |= PCI_COMMAND_MASTER |
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
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o->write(bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, x);
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o->read (bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, &x);
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o->write(bus, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0, 4, 0x00030001);
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o->read (bus, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0, 4, &x);
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#define RDP (*(volatile u32 *) 0xBE030010)
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#define RAP (*(volatile u32 *) 0xBE030014)
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#define __set_RAP(X) do { RAP = (X); x = RAP; } while (0)
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#define __set_RDP(X) do { RDP = (X); x = RDP; } while (0)
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#define __get_RDP() ({ RDP & 0xffff; })
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__set_RAP(0);
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__set_RDP(0x0004); /* CSR0 = STOP */
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__set_RAP(88); /* check CSR88 indicates an Am79C973 */
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BUG_ON(__get_RDP() != 0x5003);
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for (x = 0; x < 100; x++)
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asm volatile("nop");
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__set_RDP(0x0004); /* CSR0 = STOP */
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}
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/*
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* initialise the unit hardware
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*/
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asmlinkage void __init unit_pci_init(void)
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{
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struct pci_bus bus; /* Fake bus and device */
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struct pci_ops *o = &pci_direct_ampci;
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u32 x;
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set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_PCI_IRQ_LEVEL));
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memset(&bus, 0, sizeof(bus));
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MEM_PAGING_REG = 0xE8000000;
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/* we need to set up the bridge _now_ or we won't be able to access the
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* PCI config registers
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*/
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BRIDGEREGW(PCI_COMMAND) |=
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PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER;
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BRIDGEREGW(PCI_STATUS) = 0xF800;
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BRIDGEREGB(PCI_LATENCY_TIMER) = 0x10;
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BRIDGEREGL(PCI_BASE_ADDRESS_0) = 0x80000000;
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BRIDGEREGB(PCI_INTERRUPT_LINE) = 1;
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BRIDGEREGL(0x48) = 0x98000000; /* AMPCI base addr */
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BRIDGEREGB(0x41) = 0x00; /* secondary bus
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* number */
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BRIDGEREGB(0x42) = 0x01; /* subordinate bus
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* number */
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BRIDGEREGB(0x44) = 0x01;
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BRIDGEREGL(0x50) = 0x00000001;
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BRIDGEREGL(0x58) = 0x00001002;
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BRIDGEREGL(0x5C) = 0x00000011;
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/* we also need to set up the PCI-PCI bridge */
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bus.number = 0;
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/* IO: 0x00000000-0x00020000 */
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o->read (&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, &x);
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x |= PCI_COMMAND_MASTER |
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
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o->write(&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, x);
|
|
|
|
o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x);
|
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o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x);
|
|
o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x);
|
|
o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x);
|
|
|
|
o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, 0x01);
|
|
o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x);
|
|
o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, 0x00020000);
|
|
o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x);
|
|
o->write(&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, 0xEBB0EA00);
|
|
o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x);
|
|
o->write(&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, 0xE9F0E800);
|
|
o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x);
|
|
|
|
unit_disable_pcnet(&bus, o);
|
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}
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