mirror of https://gitee.com/openkylin/linux.git
724 lines
17 KiB
C
724 lines
17 KiB
C
/*
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* Freescale CPM1/CPM2 I2C interface.
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* Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
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*
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* moved into proper i2c interface;
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* Brad Parker (brad@heeltoe.com)
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*
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* Parts from dbox2_i2c.c (cvs.tuxbox.org)
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* (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
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*
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* (C) 2007 Montavista Software, Inc.
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* Vitaly Bordug <vitb@kernel.crashing.org>
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*
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* Converted to of_platform_device. Renamed to i2c-cpm.c.
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* (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/stddef.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <sysdev/fsl_soc.h>
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#include <asm/cpm.h>
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/* Try to define this if you have an older CPU (earlier than rev D4) */
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/* However, better use a GPIO based bitbang driver in this case :/ */
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#undef I2C_CHIP_ERRATA
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#define CPM_MAX_READ 513
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#define CPM_MAXBD 4
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#define I2C_EB (0x10) /* Big endian mode */
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#define I2C_EB_CPM2 (0x30) /* Big endian mode, memory snoop */
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#define DPRAM_BASE ((u8 __iomem __force *)cpm_muram_addr(0))
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/* I2C parameter RAM. */
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struct i2c_ram {
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ushort rbase; /* Rx Buffer descriptor base address */
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ushort tbase; /* Tx Buffer descriptor base address */
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u_char rfcr; /* Rx function code */
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u_char tfcr; /* Tx function code */
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ushort mrblr; /* Max receive buffer length */
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uint rstate; /* Internal */
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uint rdp; /* Internal */
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ushort rbptr; /* Rx Buffer descriptor pointer */
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ushort rbc; /* Internal */
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uint rxtmp; /* Internal */
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uint tstate; /* Internal */
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uint tdp; /* Internal */
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ushort tbptr; /* Tx Buffer descriptor pointer */
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ushort tbc; /* Internal */
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uint txtmp; /* Internal */
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char res1[4]; /* Reserved */
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ushort rpbase; /* Relocation pointer */
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char res2[2]; /* Reserved */
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};
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#define I2COM_START 0x80
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#define I2COM_MASTER 0x01
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#define I2CER_TXE 0x10
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#define I2CER_BUSY 0x04
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#define I2CER_TXB 0x02
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#define I2CER_RXB 0x01
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#define I2MOD_EN 0x01
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/* I2C Registers */
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struct i2c_reg {
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u8 i2mod;
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u8 res1[3];
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u8 i2add;
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u8 res2[3];
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u8 i2brg;
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u8 res3[3];
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u8 i2com;
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u8 res4[3];
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u8 i2cer;
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u8 res5[3];
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u8 i2cmr;
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};
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struct cpm_i2c {
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char *base;
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struct platform_device *ofdev;
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struct i2c_adapter adap;
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uint dp_addr;
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int version; /* CPM1=1, CPM2=2 */
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int irq;
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int cp_command;
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int freq;
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struct i2c_reg __iomem *i2c_reg;
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struct i2c_ram __iomem *i2c_ram;
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u16 i2c_addr;
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wait_queue_head_t i2c_wait;
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cbd_t __iomem *tbase;
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cbd_t __iomem *rbase;
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u_char *txbuf[CPM_MAXBD];
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u_char *rxbuf[CPM_MAXBD];
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dma_addr_t txdma[CPM_MAXBD];
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dma_addr_t rxdma[CPM_MAXBD];
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};
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static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
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{
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struct cpm_i2c *cpm;
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struct i2c_reg __iomem *i2c_reg;
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struct i2c_adapter *adap = dev_id;
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int i;
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cpm = i2c_get_adapdata(dev_id);
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i2c_reg = cpm->i2c_reg;
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/* Clear interrupt. */
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i = in_8(&i2c_reg->i2cer);
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out_8(&i2c_reg->i2cer, i);
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dev_dbg(&adap->dev, "Interrupt: %x\n", i);
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wake_up(&cpm->i2c_wait);
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return i ? IRQ_HANDLED : IRQ_NONE;
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}
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static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
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{
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struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
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/* Set up the I2C parameters in the parameter ram. */
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out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
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out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
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if (cpm->version == 1) {
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out_8(&i2c_ram->tfcr, I2C_EB);
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out_8(&i2c_ram->rfcr, I2C_EB);
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} else {
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out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
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out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
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}
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out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
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out_be32(&i2c_ram->rstate, 0);
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out_be32(&i2c_ram->rdp, 0);
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out_be16(&i2c_ram->rbptr, 0);
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out_be16(&i2c_ram->rbc, 0);
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out_be32(&i2c_ram->rxtmp, 0);
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out_be32(&i2c_ram->tstate, 0);
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out_be32(&i2c_ram->tdp, 0);
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out_be16(&i2c_ram->tbptr, 0);
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out_be16(&i2c_ram->tbc, 0);
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out_be32(&i2c_ram->txtmp, 0);
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}
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static void cpm_i2c_force_close(struct i2c_adapter *adap)
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{
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struct cpm_i2c *cpm = i2c_get_adapdata(adap);
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struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
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dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
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cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
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out_8(&i2c_reg->i2cmr, 0x00); /* Disable all interrupts */
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out_8(&i2c_reg->i2cer, 0xff);
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}
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static void cpm_i2c_parse_message(struct i2c_adapter *adap,
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struct i2c_msg *pmsg, int num, int tx, int rx)
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{
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cbd_t __iomem *tbdf;
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cbd_t __iomem *rbdf;
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u_char addr;
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u_char *tb;
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u_char *rb;
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struct cpm_i2c *cpm = i2c_get_adapdata(adap);
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tbdf = cpm->tbase + tx;
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rbdf = cpm->rbase + rx;
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addr = i2c_8bit_addr_from_msg(pmsg);
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tb = cpm->txbuf[tx];
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rb = cpm->rxbuf[rx];
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/* Align read buffer */
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rb = (u_char *) (((ulong) rb + 1) & ~1);
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tb[0] = addr; /* Device address byte w/rw flag */
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out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
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out_be16(&tbdf->cbd_sc, 0);
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if (!(pmsg->flags & I2C_M_NOSTART))
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setbits16(&tbdf->cbd_sc, BD_I2C_START);
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if (tx + 1 == num)
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setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
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if (pmsg->flags & I2C_M_RD) {
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/*
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* To read, we need an empty buffer of the proper length.
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* All that is used is the first byte for address, the remainder
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* is just used for timing (and doesn't really have to exist).
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*/
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dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
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out_be16(&rbdf->cbd_datlen, 0);
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out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
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if (rx + 1 == CPM_MAXBD)
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setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
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eieio();
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setbits16(&tbdf->cbd_sc, BD_SC_READY);
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} else {
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dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
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memcpy(tb+1, pmsg->buf, pmsg->len);
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eieio();
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setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
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}
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}
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static int cpm_i2c_check_message(struct i2c_adapter *adap,
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struct i2c_msg *pmsg, int tx, int rx)
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{
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cbd_t __iomem *tbdf;
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cbd_t __iomem *rbdf;
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u_char *tb;
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u_char *rb;
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struct cpm_i2c *cpm = i2c_get_adapdata(adap);
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tbdf = cpm->tbase + tx;
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rbdf = cpm->rbase + rx;
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tb = cpm->txbuf[tx];
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rb = cpm->rxbuf[rx];
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/* Align read buffer */
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rb = (u_char *) (((uint) rb + 1) & ~1);
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eieio();
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if (pmsg->flags & I2C_M_RD) {
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dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
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in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
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if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
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dev_dbg(&adap->dev, "I2C read; No ack\n");
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return -ENXIO;
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}
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if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
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dev_err(&adap->dev,
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"I2C read; complete but rbuf empty\n");
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return -EREMOTEIO;
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}
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if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
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dev_err(&adap->dev, "I2C read; Overrun\n");
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return -EREMOTEIO;
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}
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memcpy(pmsg->buf, rb, pmsg->len);
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} else {
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dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
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in_be16(&tbdf->cbd_sc));
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if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
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dev_dbg(&adap->dev, "I2C write; No ack\n");
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return -ENXIO;
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}
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if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
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dev_err(&adap->dev, "I2C write; Underrun\n");
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return -EIO;
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}
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if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
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dev_err(&adap->dev, "I2C write; Collision\n");
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return -EIO;
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}
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}
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return 0;
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}
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static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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struct cpm_i2c *cpm = i2c_get_adapdata(adap);
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struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
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struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
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struct i2c_msg *pmsg;
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int ret;
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int tptr;
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int rptr;
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cbd_t __iomem *tbdf;
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cbd_t __iomem *rbdf;
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/* Reset to use first buffer */
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out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
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out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
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tbdf = cpm->tbase;
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rbdf = cpm->rbase;
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tptr = 0;
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rptr = 0;
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/*
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* If there was a collision in the last i2c transaction,
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* Set I2COM_MASTER as it was cleared during collision.
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*/
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if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
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out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
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}
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while (tptr < num) {
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pmsg = &msgs[tptr];
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dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
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cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
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if (pmsg->flags & I2C_M_RD)
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rptr++;
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tptr++;
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}
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/* Start transfer now */
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/* Enable RX/TX/Error interupts */
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out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
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out_8(&i2c_reg->i2cer, 0xff); /* Clear interrupt status */
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/* Chip bug, set enable here */
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setbits8(&i2c_reg->i2mod, I2MOD_EN); /* Enable */
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/* Begin transmission */
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setbits8(&i2c_reg->i2com, I2COM_START);
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tptr = 0;
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rptr = 0;
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while (tptr < num) {
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/* Check for outstanding messages */
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dev_dbg(&adap->dev, "test ready.\n");
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pmsg = &msgs[tptr];
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if (pmsg->flags & I2C_M_RD)
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ret = wait_event_timeout(cpm->i2c_wait,
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(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
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!(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
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1 * HZ);
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else
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ret = wait_event_timeout(cpm->i2c_wait,
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!(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
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1 * HZ);
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if (ret == 0) {
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ret = -EREMOTEIO;
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dev_err(&adap->dev, "I2C transfer: timeout\n");
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goto out_err;
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}
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if (ret > 0) {
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dev_dbg(&adap->dev, "ready.\n");
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ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
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tptr++;
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if (pmsg->flags & I2C_M_RD)
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rptr++;
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if (ret)
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goto out_err;
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}
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}
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#ifdef I2C_CHIP_ERRATA
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/*
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* Chip errata, clear enable. This is not needed on rev D4 CPUs.
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* Disabling I2C too early may cause too short stop condition
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*/
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udelay(4);
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clrbits8(&i2c_reg->i2mod, I2MOD_EN);
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#endif
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return (num);
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out_err:
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cpm_i2c_force_close(adap);
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#ifdef I2C_CHIP_ERRATA
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/*
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* Chip errata, clear enable. This is not needed on rev D4 CPUs.
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*/
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clrbits8(&i2c_reg->i2mod, I2MOD_EN);
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#endif
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return ret;
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}
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static u32 cpm_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
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}
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/* -----exported algorithm data: ------------------------------------- */
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static const struct i2c_algorithm cpm_i2c_algo = {
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.master_xfer = cpm_i2c_xfer,
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.functionality = cpm_i2c_func,
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};
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/* CPM_MAX_READ is also limiting writes according to the code! */
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static struct i2c_adapter_quirks cpm_i2c_quirks = {
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.max_num_msgs = CPM_MAXBD,
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.max_read_len = CPM_MAX_READ,
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.max_write_len = CPM_MAX_READ,
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};
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static const struct i2c_adapter cpm_ops = {
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.owner = THIS_MODULE,
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.name = "i2c-cpm",
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.algo = &cpm_i2c_algo,
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.quirks = &cpm_i2c_quirks,
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};
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static int cpm_i2c_setup(struct cpm_i2c *cpm)
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{
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struct platform_device *ofdev = cpm->ofdev;
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const u32 *data;
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int len, ret, i;
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void __iomem *i2c_base;
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cbd_t __iomem *tbdf;
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cbd_t __iomem *rbdf;
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unsigned char brg;
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dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
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init_waitqueue_head(&cpm->i2c_wait);
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cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
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if (!cpm->irq)
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return -EINVAL;
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|
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/* Install interrupt handler. */
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ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
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&cpm->adap);
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if (ret)
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return ret;
|
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|
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/* I2C parameter RAM */
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i2c_base = of_iomap(ofdev->dev.of_node, 1);
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if (i2c_base == NULL) {
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ret = -EINVAL;
|
|
goto out_irq;
|
|
}
|
|
|
|
if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
|
|
|
|
/* Check for and use a microcode relocation patch. */
|
|
cpm->i2c_ram = i2c_base;
|
|
cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
|
|
|
|
/*
|
|
* Maybe should use cpm_muram_alloc instead of hardcoding
|
|
* this in micropatch.c
|
|
*/
|
|
if (cpm->i2c_addr) {
|
|
cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
|
|
iounmap(i2c_base);
|
|
}
|
|
|
|
cpm->version = 1;
|
|
|
|
} else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
|
|
cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
|
|
cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
|
|
out_be16(i2c_base, cpm->i2c_addr);
|
|
iounmap(i2c_base);
|
|
|
|
cpm->version = 2;
|
|
|
|
} else {
|
|
iounmap(i2c_base);
|
|
ret = -EINVAL;
|
|
goto out_irq;
|
|
}
|
|
|
|
/* I2C control/status registers */
|
|
cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
|
|
if (cpm->i2c_reg == NULL) {
|
|
ret = -EINVAL;
|
|
goto out_ram;
|
|
}
|
|
|
|
data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
|
|
if (!data || len != 4) {
|
|
ret = -EINVAL;
|
|
goto out_reg;
|
|
}
|
|
cpm->cp_command = *data;
|
|
|
|
data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
|
|
if (data && len == 4)
|
|
cpm->adap.class = *data;
|
|
|
|
data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
|
|
if (data && len == 4)
|
|
cpm->freq = *data;
|
|
else
|
|
cpm->freq = 60000; /* use 60kHz i2c clock by default */
|
|
|
|
/*
|
|
* Allocate space for CPM_MAXBD transmit and receive buffer
|
|
* descriptors in the DP ram.
|
|
*/
|
|
cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
|
|
if (!cpm->dp_addr) {
|
|
ret = -ENOMEM;
|
|
goto out_reg;
|
|
}
|
|
|
|
cpm->tbase = cpm_muram_addr(cpm->dp_addr);
|
|
cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
|
|
|
|
/* Allocate TX and RX buffers */
|
|
|
|
tbdf = cpm->tbase;
|
|
rbdf = cpm->rbase;
|
|
|
|
for (i = 0; i < CPM_MAXBD; i++) {
|
|
cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
|
|
CPM_MAX_READ + 1,
|
|
&cpm->rxdma[i], GFP_KERNEL);
|
|
if (!cpm->rxbuf[i]) {
|
|
ret = -ENOMEM;
|
|
goto out_muram;
|
|
}
|
|
out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
|
|
|
|
cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
|
|
if (!cpm->txbuf[i]) {
|
|
ret = -ENOMEM;
|
|
goto out_muram;
|
|
}
|
|
out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
|
|
}
|
|
|
|
/* Initialize Tx/Rx parameters. */
|
|
|
|
cpm_reset_i2c_params(cpm);
|
|
|
|
dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
|
|
cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
|
|
dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
|
|
(u8 __iomem *)cpm->tbase - DPRAM_BASE,
|
|
(u8 __iomem *)cpm->rbase - DPRAM_BASE);
|
|
|
|
cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
|
|
|
|
/*
|
|
* Select an invalid address. Just make sure we don't use loopback mode
|
|
*/
|
|
out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
|
|
|
|
/*
|
|
* PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
|
|
* i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
|
|
* the actual i2c bus frequency.
|
|
*/
|
|
brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
|
|
out_8(&cpm->i2c_reg->i2brg, brg);
|
|
|
|
out_8(&cpm->i2c_reg->i2mod, 0x00);
|
|
out_8(&cpm->i2c_reg->i2com, I2COM_MASTER); /* Master mode */
|
|
|
|
/* Disable interrupts. */
|
|
out_8(&cpm->i2c_reg->i2cmr, 0);
|
|
out_8(&cpm->i2c_reg->i2cer, 0xff);
|
|
|
|
return 0;
|
|
|
|
out_muram:
|
|
for (i = 0; i < CPM_MAXBD; i++) {
|
|
if (cpm->rxbuf[i])
|
|
dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
|
|
cpm->rxbuf[i], cpm->rxdma[i]);
|
|
if (cpm->txbuf[i])
|
|
dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
|
|
cpm->txbuf[i], cpm->txdma[i]);
|
|
}
|
|
cpm_muram_free(cpm->dp_addr);
|
|
out_reg:
|
|
iounmap(cpm->i2c_reg);
|
|
out_ram:
|
|
if ((cpm->version == 1) && (!cpm->i2c_addr))
|
|
iounmap(cpm->i2c_ram);
|
|
if (cpm->version == 2)
|
|
cpm_muram_free(cpm->i2c_addr);
|
|
out_irq:
|
|
free_irq(cpm->irq, &cpm->adap);
|
|
return ret;
|
|
}
|
|
|
|
static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
|
|
{
|
|
int i;
|
|
|
|
/* Shut down I2C. */
|
|
clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
|
|
|
|
/* Disable interrupts */
|
|
out_8(&cpm->i2c_reg->i2cmr, 0);
|
|
out_8(&cpm->i2c_reg->i2cer, 0xff);
|
|
|
|
free_irq(cpm->irq, &cpm->adap);
|
|
|
|
/* Free all memory */
|
|
for (i = 0; i < CPM_MAXBD; i++) {
|
|
dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
|
|
cpm->rxbuf[i], cpm->rxdma[i]);
|
|
dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
|
|
cpm->txbuf[i], cpm->txdma[i]);
|
|
}
|
|
|
|
cpm_muram_free(cpm->dp_addr);
|
|
iounmap(cpm->i2c_reg);
|
|
|
|
if ((cpm->version == 1) && (!cpm->i2c_addr))
|
|
iounmap(cpm->i2c_ram);
|
|
if (cpm->version == 2)
|
|
cpm_muram_free(cpm->i2c_addr);
|
|
}
|
|
|
|
static int cpm_i2c_probe(struct platform_device *ofdev)
|
|
{
|
|
int result, len;
|
|
struct cpm_i2c *cpm;
|
|
const u32 *data;
|
|
|
|
cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
|
|
if (!cpm)
|
|
return -ENOMEM;
|
|
|
|
cpm->ofdev = ofdev;
|
|
|
|
platform_set_drvdata(ofdev, cpm);
|
|
|
|
cpm->adap = cpm_ops;
|
|
i2c_set_adapdata(&cpm->adap, cpm);
|
|
cpm->adap.dev.parent = &ofdev->dev;
|
|
cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
|
|
|
|
result = cpm_i2c_setup(cpm);
|
|
if (result) {
|
|
dev_err(&ofdev->dev, "Unable to init hardware\n");
|
|
goto out_free;
|
|
}
|
|
|
|
/* register new adapter to i2c module... */
|
|
|
|
data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
|
|
cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
|
|
result = i2c_add_numbered_adapter(&cpm->adap);
|
|
|
|
if (result < 0) {
|
|
dev_err(&ofdev->dev, "Unable to register with I2C\n");
|
|
goto out_shut;
|
|
}
|
|
|
|
dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
|
|
cpm->adap.name);
|
|
|
|
return 0;
|
|
out_shut:
|
|
cpm_i2c_shutdown(cpm);
|
|
out_free:
|
|
kfree(cpm);
|
|
|
|
return result;
|
|
}
|
|
|
|
static int cpm_i2c_remove(struct platform_device *ofdev)
|
|
{
|
|
struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
|
|
|
|
i2c_del_adapter(&cpm->adap);
|
|
|
|
cpm_i2c_shutdown(cpm);
|
|
|
|
kfree(cpm);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id cpm_i2c_match[] = {
|
|
{
|
|
.compatible = "fsl,cpm1-i2c",
|
|
},
|
|
{
|
|
.compatible = "fsl,cpm2-i2c",
|
|
},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, cpm_i2c_match);
|
|
|
|
static struct platform_driver cpm_i2c_driver = {
|
|
.probe = cpm_i2c_probe,
|
|
.remove = cpm_i2c_remove,
|
|
.driver = {
|
|
.name = "fsl-i2c-cpm",
|
|
.of_match_table = cpm_i2c_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(cpm_i2c_driver);
|
|
|
|
MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
|
|
MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
|
|
MODULE_LICENSE("GPL");
|