mirror of https://gitee.com/openkylin/linux.git
902 lines
24 KiB
C
902 lines
24 KiB
C
/*
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* Synopsys DesignWare I2C adapter driver (master only).
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/export.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include "i2c-designware-core.h"
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/*
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* Registers offset
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*/
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#define DW_IC_CON 0x0
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#define DW_IC_TAR 0x4
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#define DW_IC_DATA_CMD 0x10
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#define DW_IC_SS_SCL_HCNT 0x14
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#define DW_IC_SS_SCL_LCNT 0x18
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#define DW_IC_FS_SCL_HCNT 0x1c
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#define DW_IC_FS_SCL_LCNT 0x20
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#define DW_IC_INTR_STAT 0x2c
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#define DW_IC_INTR_MASK 0x30
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#define DW_IC_RAW_INTR_STAT 0x34
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#define DW_IC_RX_TL 0x38
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#define DW_IC_TX_TL 0x3c
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#define DW_IC_CLR_INTR 0x40
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#define DW_IC_CLR_RX_UNDER 0x44
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#define DW_IC_CLR_RX_OVER 0x48
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#define DW_IC_CLR_TX_OVER 0x4c
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#define DW_IC_CLR_RD_REQ 0x50
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#define DW_IC_CLR_TX_ABRT 0x54
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#define DW_IC_CLR_RX_DONE 0x58
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#define DW_IC_CLR_ACTIVITY 0x5c
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#define DW_IC_CLR_STOP_DET 0x60
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#define DW_IC_CLR_START_DET 0x64
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#define DW_IC_CLR_GEN_CALL 0x68
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#define DW_IC_ENABLE 0x6c
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#define DW_IC_STATUS 0x70
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#define DW_IC_TXFLR 0x74
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#define DW_IC_RXFLR 0x78
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#define DW_IC_SDA_HOLD 0x7c
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#define DW_IC_TX_ABRT_SOURCE 0x80
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#define DW_IC_ENABLE_STATUS 0x9c
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#define DW_IC_COMP_PARAM_1 0xf4
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#define DW_IC_COMP_VERSION 0xf8
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#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
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#define DW_IC_COMP_TYPE 0xfc
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#define DW_IC_COMP_TYPE_VALUE 0x44570140
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#define DW_IC_INTR_RX_UNDER 0x001
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#define DW_IC_INTR_RX_OVER 0x002
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#define DW_IC_INTR_RX_FULL 0x004
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#define DW_IC_INTR_TX_OVER 0x008
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#define DW_IC_INTR_TX_EMPTY 0x010
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#define DW_IC_INTR_RD_REQ 0x020
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#define DW_IC_INTR_TX_ABRT 0x040
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#define DW_IC_INTR_RX_DONE 0x080
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#define DW_IC_INTR_ACTIVITY 0x100
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#define DW_IC_INTR_STOP_DET 0x200
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#define DW_IC_INTR_START_DET 0x400
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#define DW_IC_INTR_GEN_CALL 0x800
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#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
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DW_IC_INTR_TX_EMPTY | \
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DW_IC_INTR_TX_ABRT | \
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DW_IC_INTR_STOP_DET)
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#define DW_IC_STATUS_ACTIVITY 0x1
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#define DW_IC_ERR_TX_ABRT 0x1
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#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
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/*
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* status codes
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*/
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#define STATUS_IDLE 0x0
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#define STATUS_WRITE_IN_PROGRESS 0x1
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#define STATUS_READ_IN_PROGRESS 0x2
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#define TIMEOUT 20 /* ms */
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/*
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* hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
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*
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* only expected abort codes are listed here
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* refer to the datasheet for the full list
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*/
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#define ABRT_7B_ADDR_NOACK 0
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#define ABRT_10ADDR1_NOACK 1
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#define ABRT_10ADDR2_NOACK 2
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#define ABRT_TXDATA_NOACK 3
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#define ABRT_GCALL_NOACK 4
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#define ABRT_GCALL_READ 5
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#define ABRT_SBYTE_ACKDET 7
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#define ABRT_SBYTE_NORSTRT 9
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#define ABRT_10B_RD_NORSTRT 10
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#define ABRT_MASTER_DIS 11
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#define ARB_LOST 12
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#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
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#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
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#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
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#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
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#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
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#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
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#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
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#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
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#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
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#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
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#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
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#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
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DW_IC_TX_ABRT_10ADDR1_NOACK | \
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DW_IC_TX_ABRT_10ADDR2_NOACK | \
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DW_IC_TX_ABRT_TXDATA_NOACK | \
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DW_IC_TX_ABRT_GCALL_NOACK)
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static char *abort_sources[] = {
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[ABRT_7B_ADDR_NOACK] =
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"slave address not acknowledged (7bit mode)",
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[ABRT_10ADDR1_NOACK] =
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"first address byte not acknowledged (10bit mode)",
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[ABRT_10ADDR2_NOACK] =
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"second address byte not acknowledged (10bit mode)",
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[ABRT_TXDATA_NOACK] =
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"data not acknowledged",
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[ABRT_GCALL_NOACK] =
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"no acknowledgement for a general call",
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[ABRT_GCALL_READ] =
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"read after general call",
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[ABRT_SBYTE_ACKDET] =
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"start byte acknowledged",
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[ABRT_SBYTE_NORSTRT] =
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"trying to send start byte when restart is disabled",
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[ABRT_10B_RD_NORSTRT] =
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"trying to read when restart is disabled (10bit mode)",
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[ABRT_MASTER_DIS] =
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"trying to use disabled adapter",
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[ARB_LOST] =
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"lost arbitration",
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};
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static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
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{
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u32 value;
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if (dev->accessor_flags & ACCESS_16BIT)
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value = readw_relaxed(dev->base + offset) |
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(readw_relaxed(dev->base + offset + 2) << 16);
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else
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value = readl_relaxed(dev->base + offset);
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if (dev->accessor_flags & ACCESS_SWAP)
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return swab32(value);
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else
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return value;
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}
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static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
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{
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if (dev->accessor_flags & ACCESS_SWAP)
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b = swab32(b);
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if (dev->accessor_flags & ACCESS_16BIT) {
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writew_relaxed((u16)b, dev->base + offset);
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writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
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} else {
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writel_relaxed(b, dev->base + offset);
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}
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}
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static u32
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i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
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{
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/*
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* DesignWare I2C core doesn't seem to have solid strategy to meet
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* the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
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* will result in violation of the tHD;STA spec.
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*/
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if (cond)
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
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*
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* This is based on the DW manuals, and represents an ideal
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* configuration. The resulting I2C bus speed will be
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* faster than any of the others.
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*
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* If your hardware is free from tHD;STA issue, try this one.
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*/
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return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
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else
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
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*
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* This is just experimental rule; the tHD;STA period turned
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* out to be proportinal to (_HCNT + 3). With this setting,
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* we could meet both tHIGH and tHD;STA timing specs.
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*
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* If unsure, you'd better to take this alternative.
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*
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* The reason why we need to take into account "tf" here,
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* is the same as described in i2c_dw_scl_lcnt().
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*/
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return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
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- 3 + offset;
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}
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static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
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{
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
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*
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* DW I2C core starts counting the SCL CNTs for the LOW period
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* of the SCL clock (tLOW) as soon as it pulls the SCL line.
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* In order to meet the tLOW timing spec, we need to take into
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* account the fall time of SCL signal (tf). Default tf value
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* should be 0.3 us, for safety.
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*/
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return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
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}
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static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
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{
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int timeout = 100;
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do {
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dw_writel(dev, enable, DW_IC_ENABLE);
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if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
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return;
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/*
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* Wait 10 times the signaling period of the highest I2C
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* transfer supported by the driver (for 400KHz this is
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* 25us) as described in the DesignWare I2C databook.
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*/
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usleep_range(25, 250);
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} while (timeout--);
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dev_warn(dev->dev, "timeout in %sabling adapter\n",
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enable ? "en" : "dis");
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}
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static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
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{
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/*
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* Clock is not necessary if we got LCNT/HCNT values directly from
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* the platform code.
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*/
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if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
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return 0;
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return dev->get_clk_rate_khz(dev);
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}
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/**
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* i2c_dw_init() - initialize the designware i2c master hardware
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* @dev: device private data
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*
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* This functions configures and enables the I2C master.
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* This function is called during I2C init function, and in case of timeout at
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* run time.
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*/
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int i2c_dw_init(struct dw_i2c_dev *dev)
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{
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u32 hcnt, lcnt;
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u32 reg;
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u32 sda_falling_time, scl_falling_time;
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int ret;
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if (dev->acquire_lock) {
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ret = dev->acquire_lock(dev);
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if (ret) {
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dev_err(dev->dev, "couldn't acquire bus ownership\n");
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return ret;
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}
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}
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reg = dw_readl(dev, DW_IC_COMP_TYPE);
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if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
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/* Configure register endianess access */
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dev->accessor_flags |= ACCESS_SWAP;
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} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
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/* Configure register access mode 16bit */
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dev->accessor_flags |= ACCESS_16BIT;
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} else if (reg != DW_IC_COMP_TYPE_VALUE) {
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dev_err(dev->dev, "Unknown Synopsys component type: "
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"0x%08x\n", reg);
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if (dev->release_lock)
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dev->release_lock(dev);
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return -ENODEV;
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}
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/* Disable the adapter */
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__i2c_dw_enable(dev, false);
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/* set standard and fast speed deviders for high/low periods */
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sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
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scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
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/* Set SCL timing parameters for standard-mode */
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if (dev->ss_hcnt && dev->ss_lcnt) {
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hcnt = dev->ss_hcnt;
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lcnt = dev->ss_lcnt;
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} else {
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hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
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4000, /* tHD;STA = tHIGH = 4.0 us */
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sda_falling_time,
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
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4700, /* tLOW = 4.7 us */
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scl_falling_time,
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0); /* No offset */
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}
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dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
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dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
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/* Set SCL timing parameters for fast-mode */
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if (dev->fs_hcnt && dev->fs_lcnt) {
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hcnt = dev->fs_hcnt;
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lcnt = dev->fs_lcnt;
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} else {
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hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
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600, /* tHD;STA = tHIGH = 0.6 us */
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sda_falling_time,
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
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1300, /* tLOW = 1.3 us */
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scl_falling_time,
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0); /* No offset */
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}
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dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
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dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
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/* Configure SDA Hold Time if required */
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if (dev->sda_hold_time) {
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reg = dw_readl(dev, DW_IC_COMP_VERSION);
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if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
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dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
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else
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dev_warn(dev->dev,
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"Hardware too old to adjust SDA hold time.");
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}
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/* Configure Tx/Rx FIFO threshold levels */
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dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
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dw_writel(dev, 0, DW_IC_RX_TL);
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/* configure the i2c master */
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dw_writel(dev, dev->master_cfg , DW_IC_CON);
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if (dev->release_lock)
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dev->release_lock(dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(i2c_dw_init);
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/*
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* Waiting for bus not busy
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*/
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static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
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{
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int timeout = TIMEOUT;
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while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
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if (timeout <= 0) {
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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return -ETIMEDOUT;
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}
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timeout--;
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usleep_range(1000, 1100);
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}
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return 0;
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}
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static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 ic_con, ic_tar = 0;
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/* Disable the adapter */
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__i2c_dw_enable(dev, false);
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/* if the slave address is ten bit address, enable 10BITADDR */
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ic_con = dw_readl(dev, DW_IC_CON);
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
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ic_con |= DW_IC_CON_10BITADDR_MASTER;
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/*
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* If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
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* mode has to be enabled via bit 12 of IC_TAR register.
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* We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
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* detected from registers.
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*/
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ic_tar = DW_IC_TAR_10BITADDR_MASTER;
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} else {
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ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
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}
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dw_writel(dev, ic_con, DW_IC_CON);
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/*
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* Set the slave (target) address and enable 10-bit addressing mode
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* if applicable.
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*/
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dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
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/* enforce disabled interrupts (due to HW issues) */
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i2c_dw_disable_int(dev);
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/* Enable the adapter */
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__i2c_dw_enable(dev, true);
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/* Clear and enable interrupts */
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dw_readl(dev, DW_IC_CLR_INTR);
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dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
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}
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/*
|
|
* Initiate (and continue) low level master read/write transaction.
|
|
* This function is only called from i2c_dw_isr, and pumping i2c_msg
|
|
* messages into the tx buffer. Even if the size of i2c_msg data is
|
|
* longer than the size of the tx buffer, it handles everything.
|
|
*/
|
|
static void
|
|
i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_msg *msgs = dev->msgs;
|
|
u32 intr_mask;
|
|
int tx_limit, rx_limit;
|
|
u32 addr = msgs[dev->msg_write_idx].addr;
|
|
u32 buf_len = dev->tx_buf_len;
|
|
u8 *buf = dev->tx_buf;
|
|
bool need_restart = false;
|
|
|
|
intr_mask = DW_IC_INTR_DEFAULT_MASK;
|
|
|
|
for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
|
|
/*
|
|
* if target address has changed, we need to
|
|
* reprogram the target address in the i2c
|
|
* adapter when we are done with this transfer
|
|
*/
|
|
if (msgs[dev->msg_write_idx].addr != addr) {
|
|
dev_err(dev->dev,
|
|
"%s: invalid target address\n", __func__);
|
|
dev->msg_err = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
if (msgs[dev->msg_write_idx].len == 0) {
|
|
dev_err(dev->dev,
|
|
"%s: invalid message length\n", __func__);
|
|
dev->msg_err = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
|
|
/* new i2c_msg */
|
|
buf = msgs[dev->msg_write_idx].buf;
|
|
buf_len = msgs[dev->msg_write_idx].len;
|
|
|
|
/* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
|
|
* IC_RESTART_EN are set, we must manually
|
|
* set restart bit between messages.
|
|
*/
|
|
if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
|
|
(dev->msg_write_idx > 0))
|
|
need_restart = true;
|
|
}
|
|
|
|
tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
|
|
rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
|
|
|
|
while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
|
|
u32 cmd = 0;
|
|
|
|
/*
|
|
* If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
|
|
* manually set the stop bit. However, it cannot be
|
|
* detected from the registers so we set it always
|
|
* when writing/reading the last byte.
|
|
*/
|
|
if (dev->msg_write_idx == dev->msgs_num - 1 &&
|
|
buf_len == 1)
|
|
cmd |= BIT(9);
|
|
|
|
if (need_restart) {
|
|
cmd |= BIT(10);
|
|
need_restart = false;
|
|
}
|
|
|
|
if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
|
|
|
|
/* avoid rx buffer overrun */
|
|
if (rx_limit - dev->rx_outstanding <= 0)
|
|
break;
|
|
|
|
dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
|
|
rx_limit--;
|
|
dev->rx_outstanding++;
|
|
} else
|
|
dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
|
|
tx_limit--; buf_len--;
|
|
}
|
|
|
|
dev->tx_buf = buf;
|
|
dev->tx_buf_len = buf_len;
|
|
|
|
if (buf_len > 0) {
|
|
/* more bytes to be written */
|
|
dev->status |= STATUS_WRITE_IN_PROGRESS;
|
|
break;
|
|
} else
|
|
dev->status &= ~STATUS_WRITE_IN_PROGRESS;
|
|
}
|
|
|
|
/*
|
|
* If i2c_msg index search is completed, we don't need TX_EMPTY
|
|
* interrupt any more.
|
|
*/
|
|
if (dev->msg_write_idx == dev->msgs_num)
|
|
intr_mask &= ~DW_IC_INTR_TX_EMPTY;
|
|
|
|
if (dev->msg_err)
|
|
intr_mask = 0;
|
|
|
|
dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
|
|
}
|
|
|
|
static void
|
|
i2c_dw_read(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_msg *msgs = dev->msgs;
|
|
int rx_valid;
|
|
|
|
for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
|
|
u32 len;
|
|
u8 *buf;
|
|
|
|
if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
|
|
continue;
|
|
|
|
if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
|
|
len = msgs[dev->msg_read_idx].len;
|
|
buf = msgs[dev->msg_read_idx].buf;
|
|
} else {
|
|
len = dev->rx_buf_len;
|
|
buf = dev->rx_buf;
|
|
}
|
|
|
|
rx_valid = dw_readl(dev, DW_IC_RXFLR);
|
|
|
|
for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
|
|
*buf++ = dw_readl(dev, DW_IC_DATA_CMD);
|
|
dev->rx_outstanding--;
|
|
}
|
|
|
|
if (len > 0) {
|
|
dev->status |= STATUS_READ_IN_PROGRESS;
|
|
dev->rx_buf_len = len;
|
|
dev->rx_buf = buf;
|
|
return;
|
|
} else
|
|
dev->status &= ~STATUS_READ_IN_PROGRESS;
|
|
}
|
|
}
|
|
|
|
static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
|
|
{
|
|
unsigned long abort_source = dev->abort_source;
|
|
int i;
|
|
|
|
if (abort_source & DW_IC_TX_ABRT_NOACK) {
|
|
for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
|
|
dev_dbg(dev->dev,
|
|
"%s: %s\n", __func__, abort_sources[i]);
|
|
return -EREMOTEIO;
|
|
}
|
|
|
|
for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
|
|
dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
|
|
|
|
if (abort_source & DW_IC_TX_ARB_LOST)
|
|
return -EAGAIN;
|
|
else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
|
|
return -EINVAL; /* wrong msgs[] data */
|
|
else
|
|
return -EIO;
|
|
}
|
|
|
|
/*
|
|
* Prepare controller for a transaction and call i2c_dw_xfer_msg
|
|
*/
|
|
static int
|
|
i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
|
{
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
int ret;
|
|
|
|
dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
|
|
|
|
pm_runtime_get_sync(dev->dev);
|
|
|
|
reinit_completion(&dev->cmd_complete);
|
|
dev->msgs = msgs;
|
|
dev->msgs_num = num;
|
|
dev->cmd_err = 0;
|
|
dev->msg_write_idx = 0;
|
|
dev->msg_read_idx = 0;
|
|
dev->msg_err = 0;
|
|
dev->status = STATUS_IDLE;
|
|
dev->abort_source = 0;
|
|
dev->rx_outstanding = 0;
|
|
|
|
if (dev->acquire_lock) {
|
|
ret = dev->acquire_lock(dev);
|
|
if (ret) {
|
|
dev_err(dev->dev, "couldn't acquire bus ownership\n");
|
|
goto done_nolock;
|
|
}
|
|
}
|
|
|
|
ret = i2c_dw_wait_bus_not_busy(dev);
|
|
if (ret < 0)
|
|
goto done;
|
|
|
|
/* start the transfers */
|
|
i2c_dw_xfer_init(dev);
|
|
|
|
/* wait for tx to complete */
|
|
if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
|
|
dev_err(dev->dev, "controller timed out\n");
|
|
/* i2c_dw_init implicitly disables the adapter */
|
|
i2c_dw_init(dev);
|
|
ret = -ETIMEDOUT;
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* We must disable the adapter before returning and signaling the end
|
|
* of the current transfer. Otherwise the hardware might continue
|
|
* generating interrupts which in turn causes a race condition with
|
|
* the following transfer. Needs some more investigation if the
|
|
* additional interrupts are a hardware bug or this driver doesn't
|
|
* handle them correctly yet.
|
|
*/
|
|
__i2c_dw_enable(dev, false);
|
|
|
|
if (dev->msg_err) {
|
|
ret = dev->msg_err;
|
|
goto done;
|
|
}
|
|
|
|
/* no error */
|
|
if (likely(!dev->cmd_err)) {
|
|
ret = num;
|
|
goto done;
|
|
}
|
|
|
|
/* We have an error */
|
|
if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
|
|
ret = i2c_dw_handle_tx_abort(dev);
|
|
goto done;
|
|
}
|
|
ret = -EIO;
|
|
|
|
done:
|
|
if (dev->release_lock)
|
|
dev->release_lock(dev);
|
|
|
|
done_nolock:
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
pm_runtime_put_autosuspend(dev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static u32 i2c_dw_func(struct i2c_adapter *adap)
|
|
{
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
return dev->functionality;
|
|
}
|
|
|
|
static struct i2c_algorithm i2c_dw_algo = {
|
|
.master_xfer = i2c_dw_xfer,
|
|
.functionality = i2c_dw_func,
|
|
};
|
|
|
|
static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
|
|
{
|
|
u32 stat;
|
|
|
|
/*
|
|
* The IC_INTR_STAT register just indicates "enabled" interrupts.
|
|
* Ths unmasked raw version of interrupt status bits are available
|
|
* in the IC_RAW_INTR_STAT register.
|
|
*
|
|
* That is,
|
|
* stat = dw_readl(IC_INTR_STAT);
|
|
* equals to,
|
|
* stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
|
|
*
|
|
* The raw version might be useful for debugging purposes.
|
|
*/
|
|
stat = dw_readl(dev, DW_IC_INTR_STAT);
|
|
|
|
/*
|
|
* Do not use the IC_CLR_INTR register to clear interrupts, or
|
|
* you'll miss some interrupts, triggered during the period from
|
|
* dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
|
|
*
|
|
* Instead, use the separately-prepared IC_CLR_* registers.
|
|
*/
|
|
if (stat & DW_IC_INTR_RX_UNDER)
|
|
dw_readl(dev, DW_IC_CLR_RX_UNDER);
|
|
if (stat & DW_IC_INTR_RX_OVER)
|
|
dw_readl(dev, DW_IC_CLR_RX_OVER);
|
|
if (stat & DW_IC_INTR_TX_OVER)
|
|
dw_readl(dev, DW_IC_CLR_TX_OVER);
|
|
if (stat & DW_IC_INTR_RD_REQ)
|
|
dw_readl(dev, DW_IC_CLR_RD_REQ);
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
/*
|
|
* The IC_TX_ABRT_SOURCE register is cleared whenever
|
|
* the IC_CLR_TX_ABRT is read. Preserve it beforehand.
|
|
*/
|
|
dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
|
|
dw_readl(dev, DW_IC_CLR_TX_ABRT);
|
|
}
|
|
if (stat & DW_IC_INTR_RX_DONE)
|
|
dw_readl(dev, DW_IC_CLR_RX_DONE);
|
|
if (stat & DW_IC_INTR_ACTIVITY)
|
|
dw_readl(dev, DW_IC_CLR_ACTIVITY);
|
|
if (stat & DW_IC_INTR_STOP_DET)
|
|
dw_readl(dev, DW_IC_CLR_STOP_DET);
|
|
if (stat & DW_IC_INTR_START_DET)
|
|
dw_readl(dev, DW_IC_CLR_START_DET);
|
|
if (stat & DW_IC_INTR_GEN_CALL)
|
|
dw_readl(dev, DW_IC_CLR_GEN_CALL);
|
|
|
|
return stat;
|
|
}
|
|
|
|
/*
|
|
* Interrupt service routine. This gets called whenever an I2C interrupt
|
|
* occurs.
|
|
*/
|
|
static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
|
|
{
|
|
struct dw_i2c_dev *dev = dev_id;
|
|
u32 stat, enabled;
|
|
|
|
enabled = dw_readl(dev, DW_IC_ENABLE);
|
|
stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
|
|
dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
|
|
if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
|
|
return IRQ_NONE;
|
|
|
|
stat = i2c_dw_read_clear_intrbits(dev);
|
|
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
dev->cmd_err |= DW_IC_ERR_TX_ABRT;
|
|
dev->status = STATUS_IDLE;
|
|
|
|
/*
|
|
* Anytime TX_ABRT is set, the contents of the tx/rx
|
|
* buffers are flushed. Make sure to skip them.
|
|
*/
|
|
dw_writel(dev, 0, DW_IC_INTR_MASK);
|
|
goto tx_aborted;
|
|
}
|
|
|
|
if (stat & DW_IC_INTR_RX_FULL)
|
|
i2c_dw_read(dev);
|
|
|
|
if (stat & DW_IC_INTR_TX_EMPTY)
|
|
i2c_dw_xfer_msg(dev);
|
|
|
|
/*
|
|
* No need to modify or disable the interrupt mask here.
|
|
* i2c_dw_xfer_msg() will take care of it according to
|
|
* the current transmit status.
|
|
*/
|
|
|
|
tx_aborted:
|
|
if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
|
|
complete(&dev->cmd_complete);
|
|
else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
|
|
/* workaround to trigger pending interrupt */
|
|
stat = dw_readl(dev, DW_IC_INTR_MASK);
|
|
i2c_dw_disable_int(dev);
|
|
dw_writel(dev, stat, DW_IC_INTR_MASK);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
void i2c_dw_disable(struct dw_i2c_dev *dev)
|
|
{
|
|
/* Disable controller */
|
|
__i2c_dw_enable(dev, false);
|
|
|
|
/* Disable all interupts */
|
|
dw_writel(dev, 0, DW_IC_INTR_MASK);
|
|
dw_readl(dev, DW_IC_CLR_INTR);
|
|
}
|
|
EXPORT_SYMBOL_GPL(i2c_dw_disable);
|
|
|
|
void i2c_dw_disable_int(struct dw_i2c_dev *dev)
|
|
{
|
|
dw_writel(dev, 0, DW_IC_INTR_MASK);
|
|
}
|
|
EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
|
|
|
|
u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
|
|
{
|
|
return dw_readl(dev, DW_IC_COMP_PARAM_1);
|
|
}
|
|
EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
|
|
|
|
int i2c_dw_probe(struct dw_i2c_dev *dev)
|
|
{
|
|
struct i2c_adapter *adap = &dev->adapter;
|
|
int r;
|
|
|
|
init_completion(&dev->cmd_complete);
|
|
|
|
r = i2c_dw_init(dev);
|
|
if (r)
|
|
return r;
|
|
|
|
snprintf(adap->name, sizeof(adap->name),
|
|
"Synopsys DesignWare I2C adapter");
|
|
adap->retries = 3;
|
|
adap->algo = &i2c_dw_algo;
|
|
adap->dev.parent = dev->dev;
|
|
i2c_set_adapdata(adap, dev);
|
|
|
|
i2c_dw_disable_int(dev);
|
|
r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
|
|
IRQF_SHARED | IRQF_COND_SUSPEND,
|
|
dev_name(dev->dev), dev);
|
|
if (r) {
|
|
dev_err(dev->dev, "failure requesting irq %i: %d\n",
|
|
dev->irq, r);
|
|
return r;
|
|
}
|
|
|
|
/*
|
|
* Increment PM usage count during adapter registration in order to
|
|
* avoid possible spurious runtime suspend when adapter device is
|
|
* registered to the device core and immediate resume in case bus has
|
|
* registered I2C slaves that do I2C transfers in their probe.
|
|
*/
|
|
pm_runtime_get_noresume(dev->dev);
|
|
r = i2c_add_numbered_adapter(adap);
|
|
if (r)
|
|
dev_err(dev->dev, "failure adding adapter: %d\n", r);
|
|
pm_runtime_put_noidle(dev->dev);
|
|
|
|
return r;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i2c_dw_probe);
|
|
|
|
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
|
|
MODULE_LICENSE("GPL");
|