mirror of https://gitee.com/openkylin/linux.git
922 lines
23 KiB
C
922 lines
23 KiB
C
/*
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* Driver for the Renesas RCar I2C unit
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*
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* Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
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* Copyright (C) 2011-2015 Renesas Electronics Corporation
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*
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* Copyright (C) 2012-14 Renesas Solutions Corp.
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This file is based on the drivers/i2c/busses/i2c-sh7760.c
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* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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/* register offsets */
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#define ICSCR 0x00 /* slave ctrl */
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#define ICMCR 0x04 /* master ctrl */
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#define ICSSR 0x08 /* slave status */
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#define ICMSR 0x0C /* master status */
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#define ICSIER 0x10 /* slave irq enable */
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#define ICMIER 0x14 /* master irq enable */
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#define ICCCR 0x18 /* clock dividers */
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#define ICSAR 0x1C /* slave address */
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#define ICMAR 0x20 /* master address */
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#define ICRXTX 0x24 /* data port */
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#define ICDMAER 0x3c /* DMA enable */
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#define ICFBSCR 0x38 /* first bit setup cycle */
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/* ICSCR */
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#define SDBS (1 << 3) /* slave data buffer select */
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#define SIE (1 << 2) /* slave interface enable */
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#define GCAE (1 << 1) /* general call address enable */
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#define FNA (1 << 0) /* forced non acknowledgment */
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/* ICMCR */
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#define MDBS (1 << 7) /* non-fifo mode switch */
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#define FSCL (1 << 6) /* override SCL pin */
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#define FSDA (1 << 5) /* override SDA pin */
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#define OBPC (1 << 4) /* override pins */
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#define MIE (1 << 3) /* master if enable */
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#define TSBE (1 << 2)
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#define FSB (1 << 1) /* force stop bit */
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#define ESG (1 << 0) /* en startbit gen */
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/* ICSSR (also for ICSIER) */
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#define GCAR (1 << 6) /* general call received */
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#define STM (1 << 5) /* slave transmit mode */
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#define SSR (1 << 4) /* stop received */
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#define SDE (1 << 3) /* slave data empty */
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#define SDT (1 << 2) /* slave data transmitted */
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#define SDR (1 << 1) /* slave data received */
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#define SAR (1 << 0) /* slave addr received */
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/* ICMSR (also for ICMIE) */
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#define MNR (1 << 6) /* nack received */
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#define MAL (1 << 5) /* arbitration lost */
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#define MST (1 << 4) /* sent a stop */
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#define MDE (1 << 3)
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#define MDT (1 << 2)
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#define MDR (1 << 1)
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#define MAT (1 << 0) /* slave addr xfer done */
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/* ICDMAER */
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#define RSDMAE (1 << 3) /* DMA Slave Received Enable */
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#define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */
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#define RMDMAE (1 << 1) /* DMA Master Received Enable */
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#define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
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/* ICFBSCR */
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#define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */
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#define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
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#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
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#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
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#define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
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#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
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#define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
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#define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
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#define RCAR_IRQ_STOP (MST)
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#define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF)
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#define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF)
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#define ID_LAST_MSG (1 << 0)
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#define ID_FIRST_MSG (1 << 1)
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#define ID_DONE (1 << 2)
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#define ID_ARBLOST (1 << 3)
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#define ID_NACK (1 << 4)
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/* persistent flags */
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#define ID_P_PM_BLOCKED (1 << 31)
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#define ID_P_MASK ID_P_PM_BLOCKED
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enum rcar_i2c_type {
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I2C_RCAR_GEN1,
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I2C_RCAR_GEN2,
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I2C_RCAR_GEN3,
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};
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struct rcar_i2c_priv {
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void __iomem *io;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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int msgs_left;
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struct clk *clk;
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wait_queue_head_t wait;
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int pos;
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u32 icccr;
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u32 flags;
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enum rcar_i2c_type devtype;
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struct i2c_client *slave;
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struct resource *res;
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struct dma_chan *dma_tx;
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struct dma_chan *dma_rx;
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struct scatterlist sg;
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enum dma_data_direction dma_direction;
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};
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#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
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#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
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#define LOOP_TIMEOUT 1024
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static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
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{
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writel(val, priv->io + reg);
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}
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static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
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{
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return readl(priv->io + reg);
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}
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static void rcar_i2c_init(struct rcar_i2c_priv *priv)
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{
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/* reset master mode */
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rcar_i2c_write(priv, ICMIER, 0);
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rcar_i2c_write(priv, ICMCR, MDBS);
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rcar_i2c_write(priv, ICMSR, 0);
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/* start clock */
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rcar_i2c_write(priv, ICCCR, priv->icccr);
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}
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static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
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{
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int i;
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for (i = 0; i < LOOP_TIMEOUT; i++) {
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/* make sure that bus is not busy */
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if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
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return 0;
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udelay(1);
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}
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return -EBUSY;
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}
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static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
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{
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u32 scgd, cdf, round, ick, sum, scl, cdf_width;
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unsigned long rate;
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struct device *dev = rcar_i2c_priv_to_dev(priv);
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/* Fall back to previously used values if not supplied */
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t->bus_freq_hz = t->bus_freq_hz ?: 100000;
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t->scl_fall_ns = t->scl_fall_ns ?: 35;
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t->scl_rise_ns = t->scl_rise_ns ?: 200;
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t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
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switch (priv->devtype) {
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case I2C_RCAR_GEN1:
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cdf_width = 2;
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break;
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case I2C_RCAR_GEN2:
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case I2C_RCAR_GEN3:
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cdf_width = 3;
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break;
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default:
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dev_err(dev, "device type error\n");
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return -EIO;
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}
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/*
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* calculate SCL clock
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* see
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* ICCCR
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*
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* ick = clkp / (1 + CDF)
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* ick : I2C internal clock < 20 MHz
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* ticf : I2C SCL falling time
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* tr : I2C SCL rising time
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* intd : LSI internal delay
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* clkp : peripheral_clk
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* F[] : integer up-valuation
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*/
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rate = clk_get_rate(priv->clk);
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cdf = rate / 20000000;
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if (cdf >= 1U << cdf_width) {
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dev_err(dev, "Input clock %lu too high\n", rate);
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return -EIO;
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}
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ick = rate / (cdf + 1);
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/*
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* it is impossible to calculate large scale
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* number on u32. separate it
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*
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* F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
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* = F[sum * ick / 1000000000]
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* = F[(ick / 1000000) * sum / 1000]
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*/
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sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
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round = (ick + 500000) / 1000000 * sum;
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round = (round + 500) / 1000;
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/*
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* Calculation result (= SCL) should be less than
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* bus_speed for hardware safety
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*
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* We could use something along the lines of
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* div = ick / (bus_speed + 1) + 1;
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* scgd = (div - 20 - round + 7) / 8;
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* scl = ick / (20 + (scgd * 8) + round);
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* (not fully verified) but that would get pretty involved
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*/
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for (scgd = 0; scgd < 0x40; scgd++) {
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scl = ick / (20 + (scgd * 8) + round);
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if (scl <= t->bus_freq_hz)
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goto scgd_find;
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}
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dev_err(dev, "it is impossible to calculate best SCL\n");
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return -EIO;
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scgd_find:
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dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
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scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
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/* keep icccr value */
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priv->icccr = scgd << cdf_width | cdf;
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return 0;
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}
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static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
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{
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int read = !!rcar_i2c_is_recv(priv);
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priv->pos = 0;
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if (priv->msgs_left == 1)
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priv->flags |= ID_LAST_MSG;
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rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
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/*
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* We don't have a testcase but the HW engineers say that the write order
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* of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
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* it didn't cause a drawback for me, let's rather be safe than sorry.
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*/
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if (priv->flags & ID_FIRST_MSG) {
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rcar_i2c_write(priv, ICMSR, 0);
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
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} else {
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
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rcar_i2c_write(priv, ICMSR, 0);
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}
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rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
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}
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static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
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{
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priv->msg++;
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priv->msgs_left--;
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priv->flags &= ID_P_MASK;
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rcar_i2c_prepare_msg(priv);
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}
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/*
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* interrupt functions
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*/
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static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
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{
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struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
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? priv->dma_rx : priv->dma_tx;
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/* Disable DMA Master Received/Transmitted */
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rcar_i2c_write(priv, ICDMAER, 0);
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/* Reset default delay */
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rcar_i2c_write(priv, ICFBSCR, TCYC06);
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dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
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priv->msg->len, priv->dma_direction);
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priv->dma_direction = DMA_NONE;
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}
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static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
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{
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if (priv->dma_direction == DMA_NONE)
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return;
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else if (priv->dma_direction == DMA_FROM_DEVICE)
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dmaengine_terminate_all(priv->dma_rx);
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else if (priv->dma_direction == DMA_TO_DEVICE)
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dmaengine_terminate_all(priv->dma_tx);
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rcar_i2c_dma_unmap(priv);
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}
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static void rcar_i2c_dma_callback(void *data)
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{
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struct rcar_i2c_priv *priv = data;
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priv->pos += sg_dma_len(&priv->sg);
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rcar_i2c_dma_unmap(priv);
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}
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static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
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{
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struct device *dev = rcar_i2c_priv_to_dev(priv);
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struct i2c_msg *msg = priv->msg;
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bool read = msg->flags & I2C_M_RD;
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enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
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struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
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struct dma_async_tx_descriptor *txdesc;
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dma_addr_t dma_addr;
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dma_cookie_t cookie;
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unsigned char *buf;
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int len;
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/* Do not use DMA if it's not available or for messages < 8 bytes */
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if (IS_ERR(chan) || msg->len < 8)
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return;
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if (read) {
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/*
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* The last two bytes needs to be fetched using PIO in
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* order for the STOP phase to work.
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*/
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buf = priv->msg->buf;
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len = priv->msg->len - 2;
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} else {
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/*
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* First byte in message was sent using PIO.
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*/
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buf = priv->msg->buf + 1;
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len = priv->msg->len - 1;
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}
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dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
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if (dma_mapping_error(dev, dma_addr)) {
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dev_dbg(dev, "dma map failed, using PIO\n");
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return;
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}
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sg_dma_len(&priv->sg) = len;
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sg_dma_address(&priv->sg) = dma_addr;
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priv->dma_direction = dir;
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txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
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read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc) {
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dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
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rcar_i2c_cleanup_dma(priv);
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return;
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}
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txdesc->callback = rcar_i2c_dma_callback;
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txdesc->callback_param = priv;
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cookie = dmaengine_submit(txdesc);
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if (dma_submit_error(cookie)) {
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dev_dbg(dev, "submitting dma failed, using PIO\n");
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rcar_i2c_cleanup_dma(priv);
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return;
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}
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/* Set delay for DMA operations */
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rcar_i2c_write(priv, ICFBSCR, TCYC17);
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/* Enable DMA Master Received/Transmitted */
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if (read)
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rcar_i2c_write(priv, ICDMAER, RMDMAE);
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else
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rcar_i2c_write(priv, ICDMAER, TMDMAE);
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dma_async_issue_pending(chan);
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}
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static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
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{
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struct i2c_msg *msg = priv->msg;
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/* FIXME: sometimes, unknown interrupt happened. Do nothing */
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if (!(msr & MDE))
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return;
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if (priv->pos < msg->len) {
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/*
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* Prepare next data to ICRXTX register.
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* This data will go to _SHIFT_ register.
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*
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* *
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* [ICRXTX] -> [SHIFT] -> [I2C bus]
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*/
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rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
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priv->pos++;
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/*
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* Try to use DMA to transmit the rest of the data if
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* address transfer pashe just finished.
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*/
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if (msr & MAT)
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rcar_i2c_dma(priv);
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} else {
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/*
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* The last data was pushed to ICRXTX on _PREV_ empty irq.
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* It is on _SHIFT_ register, and will sent to I2C bus.
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*
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* *
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* [ICRXTX] -> [SHIFT] -> [I2C bus]
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*/
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if (priv->flags & ID_LAST_MSG) {
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/*
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* If current msg is the _LAST_ msg,
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* prepare stop condition here.
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* ID_DONE will be set on STOP irq.
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*/
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
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} else {
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rcar_i2c_next_msg(priv);
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return;
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}
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}
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rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
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}
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static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
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{
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struct i2c_msg *msg = priv->msg;
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|
|
/* FIXME: sometimes, unknown interrupt happened. Do nothing */
|
|
if (!(msr & MDR))
|
|
return;
|
|
|
|
if (msr & MAT) {
|
|
/*
|
|
* Address transfer phase finished, but no data at this point.
|
|
* Try to use DMA to receive data.
|
|
*/
|
|
rcar_i2c_dma(priv);
|
|
} else if (priv->pos < msg->len) {
|
|
/* get received data */
|
|
msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
|
|
priv->pos++;
|
|
}
|
|
|
|
/*
|
|
* If next received data is the _LAST_, go to STOP phase. Might be
|
|
* overwritten by REP START when setting up a new msg. Not elegant
|
|
* but the only stable sequence for REP START I have found so far.
|
|
*/
|
|
if (priv->pos + 1 >= msg->len)
|
|
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
|
|
|
|
if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
|
|
rcar_i2c_next_msg(priv);
|
|
else
|
|
rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
|
|
}
|
|
|
|
static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
|
|
{
|
|
u32 ssr_raw, ssr_filtered;
|
|
u8 value;
|
|
|
|
ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
|
|
ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
|
|
|
|
if (!ssr_filtered)
|
|
return false;
|
|
|
|
/* address detected */
|
|
if (ssr_filtered & SAR) {
|
|
/* read or write request */
|
|
if (ssr_raw & STM) {
|
|
i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
|
|
rcar_i2c_write(priv, ICRXTX, value);
|
|
rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
|
|
} else {
|
|
i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
|
|
rcar_i2c_read(priv, ICRXTX); /* dummy read */
|
|
rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
|
|
}
|
|
|
|
rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
|
|
}
|
|
|
|
/* master sent stop */
|
|
if (ssr_filtered & SSR) {
|
|
i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
|
|
rcar_i2c_write(priv, ICSIER, SAR | SSR);
|
|
rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
|
|
}
|
|
|
|
/* master wants to write to us */
|
|
if (ssr_filtered & SDR) {
|
|
int ret;
|
|
|
|
value = rcar_i2c_read(priv, ICRXTX);
|
|
ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
|
|
/* Send NACK in case of error */
|
|
rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
|
|
rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
|
|
}
|
|
|
|
/* master wants to read from us */
|
|
if (ssr_filtered & SDE) {
|
|
i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
|
|
rcar_i2c_write(priv, ICRXTX, value);
|
|
rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
|
|
{
|
|
struct rcar_i2c_priv *priv = ptr;
|
|
u32 msr, val;
|
|
|
|
/* Clear START or STOP as soon as we can */
|
|
val = rcar_i2c_read(priv, ICMCR);
|
|
rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
|
|
|
|
msr = rcar_i2c_read(priv, ICMSR);
|
|
|
|
/* Only handle interrupts that are currently enabled */
|
|
msr &= rcar_i2c_read(priv, ICMIER);
|
|
if (!msr) {
|
|
if (rcar_i2c_slave_irq(priv))
|
|
return IRQ_HANDLED;
|
|
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
/* Arbitration lost */
|
|
if (msr & MAL) {
|
|
priv->flags |= ID_DONE | ID_ARBLOST;
|
|
goto out;
|
|
}
|
|
|
|
/* Nack */
|
|
if (msr & MNR) {
|
|
/* HW automatically sends STOP after received NACK */
|
|
rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
|
|
priv->flags |= ID_NACK;
|
|
goto out;
|
|
}
|
|
|
|
/* Stop */
|
|
if (msr & MST) {
|
|
priv->msgs_left--; /* The last message also made it */
|
|
priv->flags |= ID_DONE;
|
|
goto out;
|
|
}
|
|
|
|
if (rcar_i2c_is_recv(priv))
|
|
rcar_i2c_irq_recv(priv, msr);
|
|
else
|
|
rcar_i2c_irq_send(priv, msr);
|
|
|
|
out:
|
|
if (priv->flags & ID_DONE) {
|
|
rcar_i2c_write(priv, ICMIER, 0);
|
|
rcar_i2c_write(priv, ICMSR, 0);
|
|
wake_up(&priv->wait);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
|
|
enum dma_transfer_direction dir,
|
|
dma_addr_t port_addr)
|
|
{
|
|
struct dma_chan *chan;
|
|
struct dma_slave_config cfg;
|
|
char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
|
|
int ret;
|
|
|
|
chan = dma_request_chan(dev, chan_name);
|
|
if (IS_ERR(chan)) {
|
|
ret = PTR_ERR(chan);
|
|
dev_dbg(dev, "request_channel failed for %s (%d)\n",
|
|
chan_name, ret);
|
|
return chan;
|
|
}
|
|
|
|
memset(&cfg, 0, sizeof(cfg));
|
|
cfg.direction = dir;
|
|
if (dir == DMA_MEM_TO_DEV) {
|
|
cfg.dst_addr = port_addr;
|
|
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
} else {
|
|
cfg.src_addr = port_addr;
|
|
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
}
|
|
|
|
ret = dmaengine_slave_config(chan, &cfg);
|
|
if (ret) {
|
|
dev_dbg(dev, "slave_config failed for %s (%d)\n",
|
|
chan_name, ret);
|
|
dma_release_channel(chan);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
dev_dbg(dev, "got DMA channel for %s\n", chan_name);
|
|
return chan;
|
|
}
|
|
|
|
static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
|
|
struct i2c_msg *msg)
|
|
{
|
|
struct device *dev = rcar_i2c_priv_to_dev(priv);
|
|
bool read;
|
|
struct dma_chan *chan;
|
|
enum dma_transfer_direction dir;
|
|
|
|
read = msg->flags & I2C_M_RD;
|
|
|
|
chan = read ? priv->dma_rx : priv->dma_tx;
|
|
if (PTR_ERR(chan) != -EPROBE_DEFER)
|
|
return;
|
|
|
|
dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
|
|
chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
|
|
|
|
if (read)
|
|
priv->dma_rx = chan;
|
|
else
|
|
priv->dma_tx = chan;
|
|
}
|
|
|
|
static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
|
|
{
|
|
if (!IS_ERR(priv->dma_tx)) {
|
|
dma_release_channel(priv->dma_tx);
|
|
priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
|
|
}
|
|
|
|
if (!IS_ERR(priv->dma_rx)) {
|
|
dma_release_channel(priv->dma_rx);
|
|
priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
|
|
}
|
|
}
|
|
|
|
static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
|
|
struct i2c_msg *msgs,
|
|
int num)
|
|
{
|
|
struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
|
|
struct device *dev = rcar_i2c_priv_to_dev(priv);
|
|
int i, ret;
|
|
long time_left;
|
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
ret = rcar_i2c_bus_barrier(priv);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
/* This HW can't send STOP after address phase */
|
|
if (msgs[i].len == 0) {
|
|
ret = -EOPNOTSUPP;
|
|
goto out;
|
|
}
|
|
rcar_i2c_request_dma(priv, msgs + i);
|
|
}
|
|
|
|
/* init first message */
|
|
priv->msg = msgs;
|
|
priv->msgs_left = num;
|
|
priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
|
|
rcar_i2c_prepare_msg(priv);
|
|
|
|
time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
|
|
num * adap->timeout);
|
|
if (!time_left) {
|
|
rcar_i2c_cleanup_dma(priv);
|
|
rcar_i2c_init(priv);
|
|
ret = -ETIMEDOUT;
|
|
} else if (priv->flags & ID_NACK) {
|
|
ret = -ENXIO;
|
|
} else if (priv->flags & ID_ARBLOST) {
|
|
ret = -EAGAIN;
|
|
} else {
|
|
ret = num - priv->msgs_left; /* The number of transfer */
|
|
}
|
|
out:
|
|
pm_runtime_put(dev);
|
|
|
|
if (ret < 0 && ret != -ENXIO)
|
|
dev_err(dev, "error %d : %x\n", ret, priv->flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rcar_reg_slave(struct i2c_client *slave)
|
|
{
|
|
struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
|
|
|
|
if (priv->slave)
|
|
return -EBUSY;
|
|
|
|
if (slave->flags & I2C_CLIENT_TEN)
|
|
return -EAFNOSUPPORT;
|
|
|
|
pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
|
|
|
|
priv->slave = slave;
|
|
rcar_i2c_write(priv, ICSAR, slave->addr);
|
|
rcar_i2c_write(priv, ICSSR, 0);
|
|
rcar_i2c_write(priv, ICSIER, SAR | SSR);
|
|
rcar_i2c_write(priv, ICSCR, SIE | SDBS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rcar_unreg_slave(struct i2c_client *slave)
|
|
{
|
|
struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
|
|
|
|
WARN_ON(!priv->slave);
|
|
|
|
rcar_i2c_write(priv, ICSIER, 0);
|
|
rcar_i2c_write(priv, ICSCR, 0);
|
|
|
|
priv->slave = NULL;
|
|
|
|
pm_runtime_put(rcar_i2c_priv_to_dev(priv));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u32 rcar_i2c_func(struct i2c_adapter *adap)
|
|
{
|
|
/* This HW can't do SMBUS_QUICK and NOSTART */
|
|
return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
|
|
(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
|
}
|
|
|
|
static const struct i2c_algorithm rcar_i2c_algo = {
|
|
.master_xfer = rcar_i2c_master_xfer,
|
|
.functionality = rcar_i2c_func,
|
|
.reg_slave = rcar_reg_slave,
|
|
.unreg_slave = rcar_unreg_slave,
|
|
};
|
|
|
|
static const struct of_device_id rcar_i2c_dt_ids[] = {
|
|
{ .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
|
|
{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
|
|
{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
|
|
{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
|
|
|
|
static int rcar_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
struct rcar_i2c_priv *priv;
|
|
struct i2c_adapter *adap;
|
|
struct device *dev = &pdev->dev;
|
|
struct i2c_timings i2c_t;
|
|
int irq, ret;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(priv->clk)) {
|
|
dev_err(dev, "cannot get clock\n");
|
|
return PTR_ERR(priv->clk);
|
|
}
|
|
|
|
priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
priv->io = devm_ioremap_resource(dev, priv->res);
|
|
if (IS_ERR(priv->io))
|
|
return PTR_ERR(priv->io);
|
|
|
|
priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
|
|
init_waitqueue_head(&priv->wait);
|
|
|
|
adap = &priv->adap;
|
|
adap->nr = pdev->id;
|
|
adap->algo = &rcar_i2c_algo;
|
|
adap->class = I2C_CLASS_DEPRECATED;
|
|
adap->retries = 3;
|
|
adap->dev.parent = dev;
|
|
adap->dev.of_node = dev->of_node;
|
|
i2c_set_adapdata(adap, priv);
|
|
strlcpy(adap->name, pdev->name, sizeof(adap->name));
|
|
|
|
i2c_parse_fw_timings(dev, &i2c_t, false);
|
|
|
|
/* Init DMA */
|
|
sg_init_table(&priv->sg, 1);
|
|
priv->dma_direction = DMA_NONE;
|
|
priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
|
|
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_get_sync(dev);
|
|
ret = rcar_i2c_clock_calculate(priv, &i2c_t);
|
|
if (ret < 0)
|
|
goto out_pm_put;
|
|
|
|
rcar_i2c_init(priv);
|
|
|
|
/* Don't suspend when multi-master to keep arbitration working */
|
|
if (of_property_read_bool(dev->of_node, "multi-master"))
|
|
priv->flags |= ID_P_PM_BLOCKED;
|
|
else
|
|
pm_runtime_put(dev);
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv);
|
|
if (ret < 0) {
|
|
dev_err(dev, "cannot get irq %d\n", irq);
|
|
goto out_pm_disable;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
ret = i2c_add_numbered_adapter(adap);
|
|
if (ret < 0) {
|
|
dev_err(dev, "reg adap failed: %d\n", ret);
|
|
goto out_pm_disable;
|
|
}
|
|
|
|
dev_info(dev, "probed\n");
|
|
|
|
return 0;
|
|
|
|
out_pm_put:
|
|
pm_runtime_put(dev);
|
|
out_pm_disable:
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int rcar_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
|
|
struct device *dev = &pdev->dev;
|
|
|
|
i2c_del_adapter(&priv->adap);
|
|
rcar_i2c_release_dma(priv);
|
|
if (priv->flags & ID_P_PM_BLOCKED)
|
|
pm_runtime_put(dev);
|
|
pm_runtime_disable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver rcar_i2c_driver = {
|
|
.driver = {
|
|
.name = "i2c-rcar",
|
|
.of_match_table = rcar_i2c_dt_ids,
|
|
},
|
|
.probe = rcar_i2c_probe,
|
|
.remove = rcar_i2c_remove,
|
|
};
|
|
|
|
module_platform_driver(rcar_i2c_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
|
|
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
|