mirror of https://gitee.com/openkylin/linux.git
484 lines
13 KiB
C
484 lines
13 KiB
C
/*
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* I2C bus driver for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#define SIRFSOC_I2C_CLK_CTRL 0x00
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#define SIRFSOC_I2C_STATUS 0x0C
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#define SIRFSOC_I2C_CTRL 0x10
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#define SIRFSOC_I2C_IO_CTRL 0x14
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#define SIRFSOC_I2C_SDA_DELAY 0x18
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#define SIRFSOC_I2C_CMD_START 0x1C
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#define SIRFSOC_I2C_CMD_BUF 0x30
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#define SIRFSOC_I2C_DATA_BUF 0x80
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#define SIRFSOC_I2C_CMD_BUF_MAX 16
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#define SIRFSOC_I2C_DATA_BUF_MAX 16
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#define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
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#define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8))
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#define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8)
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#define SIRFSOC_I2C_DIV_MASK (0xFFFF)
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/* I2C status flags */
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#define SIRFSOC_I2C_STAT_BUSY BIT(0)
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#define SIRFSOC_I2C_STAT_TIP BIT(1)
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#define SIRFSOC_I2C_STAT_NACK BIT(2)
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#define SIRFSOC_I2C_STAT_TR_INT BIT(4)
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#define SIRFSOC_I2C_STAT_STOP BIT(6)
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#define SIRFSOC_I2C_STAT_CMD_DONE BIT(8)
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#define SIRFSOC_I2C_STAT_ERR BIT(9)
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#define SIRFSOC_I2C_CMD_INDEX (0x1F<<16)
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/* I2C control flags */
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#define SIRFSOC_I2C_RESET BIT(0)
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#define SIRFSOC_I2C_CORE_EN BIT(1)
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#define SIRFSOC_I2C_MASTER_MODE BIT(2)
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#define SIRFSOC_I2C_CMD_DONE_EN BIT(11)
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#define SIRFSOC_I2C_ERR_INT_EN BIT(12)
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#define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF)
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#define SIRFSOC_I2C_SCLF_FILTER (3<<8)
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#define SIRFSOC_I2C_START_CMD BIT(0)
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#define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7)
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#define SIRFSOC_I2C_NACK BIT(3)
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#define SIRFSOC_I2C_WRITE BIT(4)
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#define SIRFSOC_I2C_READ BIT(5)
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#define SIRFSOC_I2C_STOP BIT(6)
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#define SIRFSOC_I2C_START BIT(7)
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#define SIRFSOC_I2C_DEFAULT_SPEED 100000
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#define SIRFSOC_I2C_ERR_NOACK 1
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#define SIRFSOC_I2C_ERR_TIMEOUT 2
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struct sirfsoc_i2c {
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void __iomem *base;
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struct clk *clk;
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u32 cmd_ptr; /* Current position in CMD buffer */
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u8 *buf; /* Buffer passed by user */
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u32 msg_len; /* Message length */
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u32 finished_len; /* number of bytes read/written */
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u32 read_cmd_len; /* number of read cmd sent */
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int msg_read; /* 1 indicates a read message */
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int err_status; /* 1 indicates an error on bus */
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u32 sda_delay; /* For suspend/resume */
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u32 clk_div;
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int last; /* Last message in transfer, STOP cmd can be sent */
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struct completion done; /* indicates completion of message transfer */
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struct i2c_adapter adapter;
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};
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static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
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{
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u32 data = 0;
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int i;
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for (i = 0; i < siic->read_cmd_len; i++) {
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if (!(i & 0x3))
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data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
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siic->buf[siic->finished_len++] =
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(u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
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SIRFSOC_I2C_DATA_SHIFT(i));
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}
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}
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static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
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{
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u32 regval;
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int i = 0;
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if (siic->msg_read) {
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while (((siic->finished_len + i) < siic->msg_len)
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&& (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
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regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
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if (((siic->finished_len + i) ==
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(siic->msg_len - 1)) && siic->last)
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regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
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writel(regval,
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siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
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i++;
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}
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siic->read_cmd_len = i;
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} else {
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while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
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&& (siic->finished_len < siic->msg_len)) {
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regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
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if ((siic->finished_len == (siic->msg_len - 1))
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&& siic->last)
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regval |= SIRFSOC_I2C_STOP;
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writel(regval,
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siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
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writel(siic->buf[siic->finished_len++],
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siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
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}
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}
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siic->cmd_ptr = 0;
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/* Trigger the transfer */
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writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
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}
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static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
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{
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struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
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u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
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if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
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/* Error conditions */
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siic->err_status = SIRFSOC_I2C_ERR_NOACK;
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writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
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if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
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dev_dbg(&siic->adapter.dev, "ACK not received\n");
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else
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dev_err(&siic->adapter.dev, "I2C error\n");
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/*
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* Due to hardware ANOMALY, we need to reset I2C earlier after
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* we get NOACK while accessing non-existing clients, otherwise
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* we will get errors even we access existing clients later
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*/
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writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
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siic->base + SIRFSOC_I2C_CTRL);
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while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
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cpu_relax();
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complete(&siic->done);
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} else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
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/* CMD buffer execution complete */
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if (siic->msg_read)
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i2c_sirfsoc_read_data(siic);
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if (siic->finished_len == siic->msg_len)
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complete(&siic->done);
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else /* Fill a new CMD buffer for left data */
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i2c_sirfsoc_queue_cmd(siic);
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writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
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}
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return IRQ_HANDLED;
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}
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static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
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struct i2c_msg *msg)
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{
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unsigned char addr;
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u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;
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/* no data and last message -> add STOP */
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if (siic->last && (msg->len == 0))
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regval |= SIRFSOC_I2C_STOP;
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writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
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addr = i2c_8bit_addr_from_msg(msg);
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/* Reverse direction bit */
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if (msg->flags & I2C_M_REV_DIR_ADDR)
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addr ^= 1;
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writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
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}
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static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
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{
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u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
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/* timeout waiting for the xfer to finish or fail */
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int timeout = msecs_to_jiffies((msg->len + 1) * 50);
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i2c_sirfsoc_set_address(siic, msg);
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writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
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siic->base + SIRFSOC_I2C_CTRL);
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i2c_sirfsoc_queue_cmd(siic);
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if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
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siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT;
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dev_err(&siic->adapter.dev, "Transfer timeout\n");
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}
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writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
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siic->base + SIRFSOC_I2C_CTRL);
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writel(0, siic->base + SIRFSOC_I2C_CMD_START);
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/* i2c control doesn't response, reset it */
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if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) {
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writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
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siic->base + SIRFSOC_I2C_CTRL);
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while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
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cpu_relax();
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}
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return siic->err_status ? -EAGAIN : 0;
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}
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static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num)
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{
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struct sirfsoc_i2c *siic = adap->algo_data;
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int i, ret;
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clk_enable(siic->clk);
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for (i = 0; i < num; i++) {
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siic->buf = msgs[i].buf;
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siic->msg_len = msgs[i].len;
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siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
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siic->err_status = 0;
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siic->cmd_ptr = 0;
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siic->finished_len = 0;
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siic->last = (i == (num - 1));
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ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
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if (ret) {
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clk_disable(siic->clk);
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return ret;
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}
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}
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clk_disable(siic->clk);
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return num;
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}
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/* I2C algorithms associated with this master controller driver */
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static const struct i2c_algorithm i2c_sirfsoc_algo = {
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.master_xfer = i2c_sirfsoc_xfer,
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.functionality = i2c_sirfsoc_func,
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};
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static int i2c_sirfsoc_probe(struct platform_device *pdev)
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{
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struct sirfsoc_i2c *siic;
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struct i2c_adapter *adap;
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struct resource *mem_res;
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struct clk *clk;
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int bitrate;
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int ctrl_speed;
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int irq;
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int err;
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u32 regval;
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clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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err = PTR_ERR(clk);
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dev_err(&pdev->dev, "Clock get failed\n");
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goto err_get_clk;
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}
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err = clk_prepare(clk);
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if (err) {
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dev_err(&pdev->dev, "Clock prepare failed\n");
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goto err_clk_prep;
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}
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err = clk_enable(clk);
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if (err) {
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dev_err(&pdev->dev, "Clock enable failed\n");
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goto err_clk_en;
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}
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ctrl_speed = clk_get_rate(clk);
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siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
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if (!siic) {
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err = -ENOMEM;
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goto out;
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}
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adap = &siic->adapter;
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adap->class = I2C_CLASS_DEPRECATED;
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mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
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if (IS_ERR(siic->base)) {
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err = PTR_ERR(siic->base);
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goto out;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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err = irq;
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goto out;
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}
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err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
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dev_name(&pdev->dev), siic);
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if (err)
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goto out;
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adap->algo = &i2c_sirfsoc_algo;
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adap->algo_data = siic;
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adap->retries = 3;
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adap->dev.of_node = pdev->dev.of_node;
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adap->dev.parent = &pdev->dev;
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adap->nr = pdev->id;
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strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
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platform_set_drvdata(pdev, adap);
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init_completion(&siic->done);
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/* Controller Initalisation */
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writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
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while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
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cpu_relax();
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writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
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siic->base + SIRFSOC_I2C_CTRL);
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siic->clk = clk;
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err = of_property_read_u32(pdev->dev.of_node,
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"clock-frequency", &bitrate);
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if (err < 0)
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bitrate = SIRFSOC_I2C_DEFAULT_SPEED;
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/*
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* Due to some hardware design issues, we need to tune the formula.
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* Since i2c is open drain interface that allows the slave to
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* stall the transaction by holding the SCL line at '0', the RTL
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* implementation is waiting for SCL feedback from the pin after
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* setting it to High-Z ('1'). This wait adds to the high-time
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* interval counter few cycles of the input synchronization
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* (depending on the SCL_FILTER_REG field), and also the time it
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* takes for the board pull-up resistor to rise the SCL line.
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* For slow SCL settings these additions are negligible,
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* but they start to affect the speed when clock is set to faster
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* frequencies.
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* Through the actual tests, use the different user_div value(which
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* in the divider formular 'Fio / (Fi2c * user_div)') to adapt
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* the different ranges of i2c bus clock frequency, to make the SCL
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* more accurate.
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*/
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if (bitrate <= 30000)
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regval = ctrl_speed / (bitrate * 5);
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else if (bitrate > 30000 && bitrate <= 280000)
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regval = (2 * ctrl_speed) / (bitrate * 11);
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else
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regval = ctrl_speed / (bitrate * 6);
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writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
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if (regval > 0xFF)
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writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
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else
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writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
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err = i2c_add_numbered_adapter(adap);
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if (err < 0) {
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dev_err(&pdev->dev, "Can't add new i2c adapter\n");
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goto out;
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}
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clk_disable(clk);
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dev_info(&pdev->dev, " I2C adapter ready to operate\n");
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return 0;
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out:
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clk_disable(clk);
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err_clk_en:
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clk_unprepare(clk);
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err_clk_prep:
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clk_put(clk);
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err_get_clk:
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return err;
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}
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static int i2c_sirfsoc_remove(struct platform_device *pdev)
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{
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struct i2c_adapter *adapter = platform_get_drvdata(pdev);
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struct sirfsoc_i2c *siic = adapter->algo_data;
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writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
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i2c_del_adapter(adapter);
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clk_unprepare(siic->clk);
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clk_put(siic->clk);
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return 0;
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}
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#ifdef CONFIG_PM
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static int i2c_sirfsoc_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct i2c_adapter *adapter = platform_get_drvdata(pdev);
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struct sirfsoc_i2c *siic = adapter->algo_data;
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clk_enable(siic->clk);
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siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
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siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
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clk_disable(siic->clk);
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return 0;
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}
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static int i2c_sirfsoc_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct i2c_adapter *adapter = platform_get_drvdata(pdev);
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struct sirfsoc_i2c *siic = adapter->algo_data;
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clk_enable(siic->clk);
|
|
writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
|
|
while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
|
|
cpu_relax();
|
|
writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
|
|
siic->base + SIRFSOC_I2C_CTRL);
|
|
writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
|
|
writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
|
|
clk_disable(siic->clk);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
|
|
.suspend = i2c_sirfsoc_suspend,
|
|
.resume = i2c_sirfsoc_resume,
|
|
};
|
|
#endif
|
|
|
|
static const struct of_device_id sirfsoc_i2c_of_match[] = {
|
|
{ .compatible = "sirf,prima2-i2c", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
|
|
|
|
static struct platform_driver i2c_sirfsoc_driver = {
|
|
.driver = {
|
|
.name = "sirfsoc_i2c",
|
|
#ifdef CONFIG_PM
|
|
.pm = &i2c_sirfsoc_pm_ops,
|
|
#endif
|
|
.of_match_table = sirfsoc_i2c_of_match,
|
|
},
|
|
.probe = i2c_sirfsoc_probe,
|
|
.remove = i2c_sirfsoc_remove,
|
|
};
|
|
module_platform_driver(i2c_sirfsoc_driver);
|
|
|
|
MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
|
|
MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
|
|
"Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
|
|
MODULE_LICENSE("GPL v2");
|