linux/drivers/gpu/drm/i915/gt
Dongwon Kim 397049a030 drm/i915/gen11: enable support for headerless msgs
Setting bit5 (headerless msg for preemptible GPGPU context) of SAMPLER_MODE
register to enable support for the headless msgs on gen11. None of existing
use cases will be affected by this as this change makes both types of
message - headerless and w/ header supported at the same time. It also
complies with the new recommendation for the default bit value for the
next gen.

v2: rewrote commit message to include more information
v3: setting the bit in icl_ctx_workarounds_init()

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190425055005.21790-1-chris@chris-wilson.co.uk
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-05-24 10:06:26 +01:00
..
Makefile
Makefile.header-test
intel_breadcrumbs.c drm/i915: Seal races between async GPU cancellation, retirement and signaling 2019-05-08 16:02:41 +01:00
intel_context.c drm/i915: Disable semaphore busywaits on saturated systems 2019-05-04 09:18:02 +01:00
intel_context.h drm/i915: Switch back to an array of logical per-engine HW contexts 2019-04-26 18:32:11 +01:00
intel_context_types.h drm/i915: Disable semaphore busywaits on saturated systems 2019-05-04 09:18:02 +01:00
intel_engine.h drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD 2019-05-08 15:06:35 +01:00
intel_engine_cs.c drm/i915: Engine discovery query 2019-05-22 14:17:55 +01:00
intel_engine_pm.c drm/i915/execlists: Flush the tasklet on parking 2019-05-03 11:35:31 +01:00
intel_engine_pm.h drm/i915/execlists: Flush the tasklet on parking 2019-05-03 11:35:31 +01:00
intel_engine_types.h drm/i915: Engine discovery query 2019-05-22 14:17:55 +01:00
intel_gpu_commands.h
intel_gt_pm.c drm/i915: Invert the GEM wakeref hierarchy 2019-04-24 22:26:49 +01:00
intel_gt_pm.h drm/i915: Invert the GEM wakeref hierarchy 2019-04-24 22:26:49 +01:00
intel_hangcheck.c drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD 2019-05-08 15:06:35 +01:00
intel_lrc.c drm/i915/execlists: Virtual engine bonding 2019-05-22 08:40:46 +01:00
intel_lrc.h drm/i915/execlists: Virtual engine bonding 2019-05-22 08:40:46 +01:00
intel_lrc_reg.h
intel_mocs.c
intel_mocs.h
intel_reset.c drm/i915/selftests: Move some reset testcases to separate file 2019-05-23 21:52:26 +01:00
intel_reset.h drm/i915: Invert the GEM wakeref hierarchy 2019-04-24 22:26:49 +01:00
intel_ringbuffer.c drm/i915/hangcheck: Replace hangcheck.seqno with RING_HEAD 2019-05-08 15:06:35 +01:00
intel_sseu.c
intel_sseu.h
intel_workarounds.c drm/i915/gen11: enable support for headerless msgs 2019-05-24 10:06:26 +01:00
intel_workarounds.h
intel_workarounds_types.h
mock_engine.c drm/i915: Switch back to an array of logical per-engine HW contexts 2019-04-26 18:32:11 +01:00
mock_engine.h drm/i915: Split engine setup/init into two phases 2019-04-26 18:32:07 +01:00
selftest_engine_cs.c
selftest_hangcheck.c drm/i915/selftests: Split igt_atomic_reset testcase 2019-05-23 21:53:26 +01:00
selftest_lrc.c drm/i915/execlists: Virtual engine bonding 2019-05-22 08:40:46 +01:00
selftest_reset.c drm/i915/selftests: Use prepare/finish during atomic reset test 2019-05-23 21:58:36 +01:00
selftest_workarounds.c drm/i915/selftests: Verify context workarounds 2019-05-22 10:11:09 +01:00