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56 lines
1.8 KiB
Plaintext
56 lines
1.8 KiB
Plaintext
Device Tree Clock bindings for the Zynq 7000 EPP
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The Zynq EPP has several different clk providers, each with there own bindings.
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The purpose of this document is to document their usage.
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See clock_bindings.txt for more information on the generic clock bindings.
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See Chapter 25 of Zynq TRM for more information about Zynq clocks.
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== PLLs ==
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Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
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Required properties:
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- #clock-cells : shall be 0 (only one clock is output from this node)
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- compatible : "xlnx,zynq-pll"
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- reg : pair of u32 values, which are the address offsets within the SLCR
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of the relevant PLL_CTRL register and PLL_CFG register respectively
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- clocks : phandle for parent clock. should be the phandle for ps_clk
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Optional properties:
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- clock-output-names : name of the output clock
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Example:
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armpll: armpll {
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#clock-cells = <0>;
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compatible = "xlnx,zynq-pll";
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clocks = <&ps_clk>;
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reg = <0x100 0x110>;
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clock-output-names = "armpll";
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};
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== Peripheral clocks ==
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Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
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Required properties:
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- #clock-cells : shall be 1
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- compatible : "xlnx,zynq-periph-clock"
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- reg : a single u32 value, describing the offset within the SLCR where
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the CLK_CTRL register is found for this peripheral
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- clocks : phandle for parent clocks. should hold phandles for
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the IO_PLL, ARM_PLL, and DDR_PLL in order
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- clock-output-names : names of the output clock(s). For peripherals that have
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two output clocks (for example, the UART), two clocks
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should be listed.
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Example:
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uart_clk: uart_clk {
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#clock-cells = <1>;
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compatible = "xlnx,zynq-periph-clock";
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clocks = <&iopll &armpll &ddrpll>;
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reg = <0x154>;
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clock-output-names = "uart0_ref_clk",
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"uart1_ref_clk";
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};
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