mirror of https://gitee.com/openkylin/linux.git
314 lines
7.7 KiB
C
314 lines
7.7 KiB
C
/*
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* Common code for the boards based on Freescale MPC52xx embedded CPU.
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*
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*
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* Maintainer : Sylvain Munaut <tnt@246tNt.com>
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*
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* Support for other bootloaders than UBoot by Dale Farnsworth
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* <dfarnsworth@mvista.com>
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*
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* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 Montavista Software, Inc
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/spinlock.h>
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#include <asm/io.h>
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#include <asm/time.h>
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#include <asm/mpc52xx.h>
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#include <asm/mpc52xx_psc.h>
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#include <asm/pgtable.h>
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#include <asm/ppcboot.h>
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#include <syslib/mpc52xx_pci.h>
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extern bd_t __res;
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static int core_mult[] = { /* CPU Frequency multiplier, taken */
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0, 0, 0, 10, 20, 20, 25, 45, /* from the datasheet used to compute */
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30, 55, 40, 50, 0, 60, 35, 0, /* CPU frequency from XLB freq and */
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30, 25, 65, 10, 70, 20, 75, 45, /* external jumper config */
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0, 55, 40, 50, 80, 60, 35, 0
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};
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void
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mpc52xx_restart(char *cmd)
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{
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struct mpc52xx_gpt __iomem *gpt0 = MPC52xx_VA(MPC52xx_GPTx_OFFSET(0));
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local_irq_disable();
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/* Turn on the watchdog and wait for it to expire. It effectively
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does a reset */
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out_be32(&gpt0->count, 0x000000ff);
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out_be32(&gpt0->mode, 0x00009004);
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while (1);
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}
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void
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mpc52xx_halt(void)
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{
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local_irq_disable();
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while (1);
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}
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void
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mpc52xx_power_off(void)
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{
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/* By default we don't have any way of shut down.
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If a specific board wants to, it can set the power down
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code to any hardware implementation dependent code */
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mpc52xx_halt();
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}
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void __init
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mpc52xx_set_bat(void)
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{
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/* Set BAT 2 to map the 0xf0000000 area */
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/* This mapping is used during mpc52xx_progress,
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* mpc52xx_find_end_of_memory, and UARTs/GPIO access for debug
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*/
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mb();
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mtspr(SPRN_DBAT2U, 0xf0001ffe);
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mtspr(SPRN_DBAT2L, 0xf000002a);
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mb();
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}
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void __init
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mpc52xx_map_io(void)
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{
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/* Here we map the MBAR and the whole upper zone. MBAR is only
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64k but we can't map only 64k with BATs. Map the whole
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0xf0000000 range is ok and helps eventual lpb devices placed there */
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io_block_mapping(
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MPC52xx_MBAR_VIRT, MPC52xx_MBAR, 0x10000000, _PAGE_IO);
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}
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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#ifndef MPC52xx_PF_CONSOLE_PORT
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#error "mpc52xx PSC for console not selected"
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#endif
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static void
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mpc52xx_psc_putc(struct mpc52xx_psc __iomem *psc, unsigned char c)
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{
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while (!(in_be16(&psc->mpc52xx_psc_status) &
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MPC52xx_PSC_SR_TXRDY));
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out_8(&psc->mpc52xx_psc_buffer_8, c);
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}
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void
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mpc52xx_progress(char *s, unsigned short hex)
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{
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char c;
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struct mpc52xx_psc __iomem *psc;
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psc = MPC52xx_VA(MPC52xx_PSCx_OFFSET(MPC52xx_PF_CONSOLE_PORT));
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while ((c = *s++) != 0) {
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if (c == '\n')
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mpc52xx_psc_putc(psc, '\r');
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mpc52xx_psc_putc(psc, c);
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}
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mpc52xx_psc_putc(psc, '\r');
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mpc52xx_psc_putc(psc, '\n');
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}
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#endif /* CONFIG_SERIAL_TEXT_DEBUG */
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unsigned long __init
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mpc52xx_find_end_of_memory(void)
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{
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u32 ramsize = __res.bi_memsize;
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/*
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* if bootloader passed a memsize, just use it
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* else get size from sdram config registers
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*/
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if (ramsize == 0) {
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struct mpc52xx_mmap_ctl __iomem *mmap_ctl;
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u32 sdram_config_0, sdram_config_1;
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/* Temp BAT2 mapping active when this is called ! */
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mmap_ctl = MPC52xx_VA(MPC52xx_MMAP_CTL_OFFSET);
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sdram_config_0 = in_be32(&mmap_ctl->sdram0);
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sdram_config_1 = in_be32(&mmap_ctl->sdram1);
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if ((sdram_config_0 & 0x1f) >= 0x13)
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ramsize = 1 << ((sdram_config_0 & 0xf) + 17);
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if (((sdram_config_1 & 0x1f) >= 0x13) &&
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((sdram_config_1 & 0xfff00000) == ramsize))
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ramsize += 1 << ((sdram_config_1 & 0xf) + 17);
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}
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return ramsize;
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}
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void __init
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mpc52xx_calibrate_decr(void)
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{
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int current_time, previous_time;
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int tbl_start, tbl_end;
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unsigned int xlbfreq, cpufreq, ipbfreq, pcifreq, divisor;
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xlbfreq = __res.bi_busfreq;
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/* if bootloader didn't pass bus frequencies, calculate them */
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if (xlbfreq == 0) {
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/* Get RTC & Clock manager modules */
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struct mpc52xx_rtc __iomem *rtc;
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struct mpc52xx_cdm __iomem *cdm;
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rtc = ioremap(MPC52xx_PA(MPC52xx_RTC_OFFSET), MPC52xx_RTC_SIZE);
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cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
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if ((rtc==NULL) || (cdm==NULL))
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panic("Can't ioremap RTC/CDM while computing bus freq");
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/* Count bus clock during 1/64 sec */
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out_be32(&rtc->dividers, 0x8f1f0000); /* Set RTC 64x faster */
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previous_time = in_be32(&rtc->time);
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while ((current_time = in_be32(&rtc->time)) == previous_time) ;
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tbl_start = get_tbl();
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previous_time = current_time;
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while ((current_time = in_be32(&rtc->time)) == previous_time) ;
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tbl_end = get_tbl();
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out_be32(&rtc->dividers, 0xffff0000); /* Restore RTC */
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/* Compute all frequency from that & CDM settings */
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xlbfreq = (tbl_end - tbl_start) << 8;
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cpufreq = (xlbfreq * core_mult[in_be32(&cdm->rstcfg)&0x1f])/10;
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ipbfreq = (in_8(&cdm->ipb_clk_sel) & 1) ?
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xlbfreq / 2 : xlbfreq;
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switch (in_8(&cdm->pci_clk_sel) & 3) {
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case 0:
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pcifreq = ipbfreq;
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break;
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case 1:
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pcifreq = ipbfreq / 2;
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break;
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default:
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pcifreq = xlbfreq / 4;
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break;
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}
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__res.bi_busfreq = xlbfreq;
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__res.bi_intfreq = cpufreq;
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__res.bi_ipbfreq = ipbfreq;
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__res.bi_pcifreq = pcifreq;
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/* Release mapping */
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iounmap(rtc);
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iounmap(cdm);
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}
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divisor = 4;
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tb_ticks_per_jiffy = xlbfreq / HZ / divisor;
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tb_to_us = mulhwu_scale_factor(xlbfreq / divisor, 1000000);
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}
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void __init
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mpc52xx_setup_cpu(void)
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{
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struct mpc52xx_cdm __iomem *cdm;
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struct mpc52xx_xlb __iomem *xlb;
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/* Map zones */
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cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
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xlb = ioremap(MPC52xx_PA(MPC52xx_XLB_OFFSET), MPC52xx_XLB_SIZE);
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if (!cdm || !xlb) {
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printk(KERN_ERR __FILE__ ": "
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"Error while mapping CDM/XLB during "
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"mpc52xx_setup_cpu\n");
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goto unmap_regs;
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}
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/* Use internal 48 Mhz */
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out_8(&cdm->ext_48mhz_en, 0x00);
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out_8(&cdm->fd_enable, 0x01);
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if (in_be32(&cdm->rstcfg) & 0x40) /* Assumes 33Mhz clock */
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out_be16(&cdm->fd_counters, 0x0001);
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else
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out_be16(&cdm->fd_counters, 0x5555);
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/* Configure the XLB Arbiter priorities */
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out_be32(&xlb->master_pri_enable, 0xff);
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out_be32(&xlb->master_priority, 0x11111111);
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/* Enable ram snooping for 1GB window */
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out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_SNOOP);
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out_be32(&xlb->snoop_window, MPC52xx_PCI_TARGET_MEM | 0x1d);
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/* Disable XLB pipelining */
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/* (cfr errata 292. We could do this only just before ATA PIO
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transaction and re-enable it after ...) */
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out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS);
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/* Unmap reg zone */
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unmap_regs:
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if (cdm) iounmap(cdm);
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if (xlb) iounmap(xlb);
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}
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int mpc52xx_match_psc_function(int psc_idx, const char *func)
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{
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struct mpc52xx_psc_func *cf = mpc52xx_psc_functions;
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while ((cf->id != -1) && (cf->func != NULL)) {
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if ((cf->id == psc_idx) && !strcmp(cf->func,func))
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return 1;
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cf++;
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}
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return 0;
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}
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int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
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{
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static spinlock_t lock = SPIN_LOCK_UNLOCKED;
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struct mpc52xx_cdm __iomem *cdm;
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unsigned long flags;
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u16 mclken_div;
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u16 __iomem *reg;
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u32 mask;
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cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
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if (!cdm) {
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printk(KERN_ERR __FILE__ ": Error mapping CDM\n");
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return -ENODEV;
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}
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mclken_div = 0x8000 | (clkdiv & 0x1FF);
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switch (psc_id) {
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case 1: reg = &cdm->mclken_div_psc1; mask = 0x20; break;
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case 2: reg = &cdm->mclken_div_psc2; mask = 0x40; break;
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case 3: reg = &cdm->mclken_div_psc3; mask = 0x80; break;
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case 6: reg = &cdm->mclken_div_psc6; mask = 0x10; break;
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default:
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return -ENODEV;
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}
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/* Set the rate and enable the clock */
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spin_lock_irqsave(&lock, flags);
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out_be16(reg, mclken_div);
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out_be32(&cdm->clk_enables, in_be32(&cdm->clk_enables) | mask);
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spin_unlock_irqrestore(&lock, flags);
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iounmap(cdm);
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return 0;
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}
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