mirror of https://gitee.com/openkylin/linux.git
1167 lines
28 KiB
C
1167 lines
28 KiB
C
/*
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* x86 SMP booting functions
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
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* Copyright 2001 Andi Kleen, SuSE Labs.
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*
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* Much of the core SMP work is based on previous work by Thomas Radke, to
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* whom a great many thanks are extended.
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*
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* Thanks to Intel for making available several different Pentium,
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* Pentium Pro and Pentium-II/Xeon MP machines.
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* Original development of Linux SMP code supported by Caldera.
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*
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* This code is released under the GNU General Public License version 2
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*
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* Fixes
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* Felix Koop : NR_CPUS used properly
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* Jose Renau : Handle single CPU case.
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* Alan Cox : By repeated request 8) - Total BogoMIP report.
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* Greg Wright : Fix for kernel stacks panic.
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* Erich Boleyn : MP v1.4 and additional changes.
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* Matthias Sattler : Changes for 2.1 kernel map.
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* Michel Lespinasse : Changes for 2.1 kernel map.
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* Michael Chastain : Change trampoline.S to gnu as.
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* Alan Cox : Dumb bug: 'B' step PPro's are fine
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* Ingo Molnar : Added APIC timers, based on code
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* from Jose Renau
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* Ingo Molnar : various cleanups and rewrites
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* Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
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* Maciej W. Rozycki : Bits for genuine 82489DX APICs
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* Andi Kleen : Changed for SMP boot into long mode.
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* Rusty Russell : Hacked into shape for new "hotplug" boot process.
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* Andi Kleen : Converted to new state machine.
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* Various cleanups.
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* Probably mostly hotplug CPU ready now.
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* Ashok Raj : CPU hotplug support
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/kernel_stat.h>
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#include <linux/smp_lock.h>
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#include <linux/bootmem.h>
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#include <linux/thread_info.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mc146818rtc.h>
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#include <asm/mtrr.h>
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#include <asm/pgalloc.h>
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#include <asm/desc.h>
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#include <asm/kdebug.h>
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#include <asm/tlbflush.h>
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#include <asm/proto.h>
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#include <asm/nmi.h>
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#include <asm/irq.h>
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#include <asm/hw_irq.h>
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/* Number of siblings per CPU package */
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int smp_num_siblings = 1;
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/* Package ID of each logical CPU */
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u8 phys_proc_id[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
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u8 cpu_core_id[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
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EXPORT_SYMBOL(phys_proc_id);
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EXPORT_SYMBOL(cpu_core_id);
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/* Bitmask of currently online CPUs */
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cpumask_t cpu_online_map __read_mostly;
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EXPORT_SYMBOL(cpu_online_map);
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/*
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* Private maps to synchronize booting between AP and BP.
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* Probably not needed anymore, but it makes for easier debugging. -AK
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*/
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cpumask_t cpu_callin_map;
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cpumask_t cpu_callout_map;
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cpumask_t cpu_possible_map;
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EXPORT_SYMBOL(cpu_possible_map);
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/* Per CPU bogomips and other parameters */
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struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
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/* Set when the idlers are all forked */
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int smp_threads_ready;
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cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
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cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_core_map);
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/*
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* Trampoline 80x86 program as an array.
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*/
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extern unsigned char trampoline_data[];
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extern unsigned char trampoline_end[];
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/* State of each CPU */
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DEFINE_PER_CPU(int, cpu_state) = { 0 };
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/*
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* Store all idle threads, this can be reused instead of creating
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* a new thread. Also avoids complicated thread destroy functionality
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* for idle threads.
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*/
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struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
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#define get_idle_for_cpu(x) (idle_thread_array[(x)])
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#define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p))
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/*
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* Currently trivial. Write the real->protected mode
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* bootstrap into the page concerned. The caller
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* has made sure it's suitably aligned.
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*/
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static unsigned long __cpuinit setup_trampoline(void)
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{
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void *tramp = __va(SMP_TRAMPOLINE_BASE);
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memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
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return virt_to_phys(tramp);
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}
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/*
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* The bootstrap kernel entry code has set these up. Save them for
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* a given CPU
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*/
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static void __cpuinit smp_store_cpu_info(int id)
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{
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struct cpuinfo_x86 *c = cpu_data + id;
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*c = boot_cpu_data;
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identify_cpu(c);
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print_cpu_info(c);
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}
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/*
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* New Funky TSC sync algorithm borrowed from IA64.
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* Main advantage is that it doesn't reset the TSCs fully and
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* in general looks more robust and it works better than my earlier
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* attempts. I believe it was written by David Mosberger. Some minor
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* adjustments for x86-64 by me -AK
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*
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* Original comment reproduced below.
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*
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* Synchronize TSC of the current (slave) CPU with the TSC of the
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* MASTER CPU (normally the time-keeper CPU). We use a closed loop to
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* eliminate the possibility of unaccounted-for errors (such as
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* getting a machine check in the middle of a calibration step). The
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* basic idea is for the slave to ask the master what itc value it has
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* and to read its own itc before and after the master responds. Each
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* iteration gives us three timestamps:
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*
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* slave master
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*
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* t0 ---\
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* ---\
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* --->
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* tm
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* /---
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* /---
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* t1 <---
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*
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*
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* The goal is to adjust the slave's TSC such that tm falls exactly
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* half-way between t0 and t1. If we achieve this, the clocks are
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* synchronized provided the interconnect between the slave and the
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* master is symmetric. Even if the interconnect were asymmetric, we
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* would still know that the synchronization error is smaller than the
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* roundtrip latency (t0 - t1).
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*
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* When the interconnect is quiet and symmetric, this lets us
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* synchronize the TSC to within one or two cycles. However, we can
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* only *guarantee* that the synchronization is accurate to within a
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* round-trip time, which is typically in the range of several hundred
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* cycles (e.g., ~500 cycles). In practice, this means that the TSCs
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* are usually almost perfectly synchronized, but we shouldn't assume
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* that the accuracy is much better than half a micro second or so.
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*
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* [there are other errors like the latency of RDTSC and of the
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* WRMSR. These can also account to hundreds of cycles. So it's
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* probably worse. It claims 153 cycles error on a dual Opteron,
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* but I suspect the numbers are actually somewhat worse -AK]
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*/
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#define MASTER 0
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#define SLAVE (SMP_CACHE_BYTES/8)
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/* Intentionally don't use cpu_relax() while TSC synchronization
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because we don't want to go into funky power save modi or cause
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hypervisors to schedule us away. Going to sleep would likely affect
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latency and low latency is the primary objective here. -AK */
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#define no_cpu_relax() barrier()
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static __cpuinitdata DEFINE_SPINLOCK(tsc_sync_lock);
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static volatile __cpuinitdata unsigned long go[SLAVE + 1];
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static int notscsync __cpuinitdata;
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#undef DEBUG_TSC_SYNC
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#define NUM_ROUNDS 64 /* magic value */
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#define NUM_ITERS 5 /* likewise */
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/* Callback on boot CPU */
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static __cpuinit void sync_master(void *arg)
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{
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unsigned long flags, i;
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go[MASTER] = 0;
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local_irq_save(flags);
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{
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for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
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while (!go[MASTER])
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no_cpu_relax();
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go[MASTER] = 0;
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rdtscll(go[SLAVE]);
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}
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}
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local_irq_restore(flags);
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}
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/*
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* Return the number of cycles by which our tsc differs from the tsc
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* on the master (time-keeper) CPU. A positive number indicates our
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* tsc is ahead of the master, negative that it is behind.
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*/
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static inline long
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get_delta(long *rt, long *master)
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{
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unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
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unsigned long tcenter, t0, t1, tm;
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int i;
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for (i = 0; i < NUM_ITERS; ++i) {
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rdtscll(t0);
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go[MASTER] = 1;
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while (!(tm = go[SLAVE]))
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no_cpu_relax();
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go[SLAVE] = 0;
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rdtscll(t1);
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if (t1 - t0 < best_t1 - best_t0)
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best_t0 = t0, best_t1 = t1, best_tm = tm;
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}
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*rt = best_t1 - best_t0;
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*master = best_tm - best_t0;
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/* average best_t0 and best_t1 without overflow: */
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tcenter = (best_t0/2 + best_t1/2);
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if (best_t0 % 2 + best_t1 % 2 == 2)
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++tcenter;
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return tcenter - best_tm;
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}
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static __cpuinit void sync_tsc(unsigned int master)
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{
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int i, done = 0;
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long delta, adj, adjust_latency = 0;
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unsigned long flags, rt, master_time_stamp, bound;
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#ifdef DEBUG_TSC_SYNC
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static struct syncdebug {
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long rt; /* roundtrip time */
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long master; /* master's timestamp */
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long diff; /* difference between midpoint and master's timestamp */
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long lat; /* estimate of tsc adjustment latency */
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} t[NUM_ROUNDS] __cpuinitdata;
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#endif
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printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n",
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smp_processor_id(), master);
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go[MASTER] = 1;
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/* It is dangerous to broadcast IPI as cpus are coming up,
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* as they may not be ready to accept them. So since
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* we only need to send the ipi to the boot cpu direct
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* the message, and avoid the race.
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*/
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smp_call_function_single(master, sync_master, NULL, 1, 0);
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while (go[MASTER]) /* wait for master to be ready */
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no_cpu_relax();
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spin_lock_irqsave(&tsc_sync_lock, flags);
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{
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for (i = 0; i < NUM_ROUNDS; ++i) {
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delta = get_delta(&rt, &master_time_stamp);
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if (delta == 0) {
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done = 1; /* let's lock on to this... */
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bound = rt;
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}
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if (!done) {
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unsigned long t;
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if (i > 0) {
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adjust_latency += -delta;
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adj = -delta + adjust_latency/4;
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} else
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adj = -delta;
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rdtscll(t);
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wrmsrl(MSR_IA32_TSC, t + adj);
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}
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#ifdef DEBUG_TSC_SYNC
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t[i].rt = rt;
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t[i].master = master_time_stamp;
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t[i].diff = delta;
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t[i].lat = adjust_latency/4;
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#endif
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}
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}
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spin_unlock_irqrestore(&tsc_sync_lock, flags);
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#ifdef DEBUG_TSC_SYNC
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for (i = 0; i < NUM_ROUNDS; ++i)
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printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
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t[i].rt, t[i].master, t[i].diff, t[i].lat);
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#endif
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printk(KERN_INFO
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"CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, "
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"maxerr %lu cycles)\n",
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smp_processor_id(), master, delta, rt);
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}
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static void __cpuinit tsc_sync_wait(void)
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{
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if (notscsync || !cpu_has_tsc)
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return;
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sync_tsc(0);
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}
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static __init int notscsync_setup(char *s)
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{
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notscsync = 1;
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return 0;
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}
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__setup("notscsync", notscsync_setup);
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static atomic_t init_deasserted __cpuinitdata;
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/*
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* Report back to the Boot Processor.
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* Running on AP.
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*/
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void __cpuinit smp_callin(void)
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{
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int cpuid, phys_id;
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unsigned long timeout;
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/*
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* If waken up by an INIT in an 82489DX configuration
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* we may get here before an INIT-deassert IPI reaches
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* our local APIC. We have to wait for the IPI or we'll
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* lock up on an APIC access.
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*/
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while (!atomic_read(&init_deasserted))
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cpu_relax();
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/*
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* (This works even if the APIC is not enabled.)
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*/
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phys_id = GET_APIC_ID(apic_read(APIC_ID));
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cpuid = smp_processor_id();
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if (cpu_isset(cpuid, cpu_callin_map)) {
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panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
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phys_id, cpuid);
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}
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Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
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/*
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* STARTUP IPIs are fragile beasts as they might sometimes
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* trigger some glue motherboard logic. Complete APIC bus
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* silence for 1 second, this overestimates the time the
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* boot CPU is spending to send the up to 2 STARTUP IPIs
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* by a factor of two. This should be enough.
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*/
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/*
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* Waiting 2s total for startup (udelay is not yet working)
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*/
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timeout = jiffies + 2*HZ;
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while (time_before(jiffies, timeout)) {
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/*
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* Has the boot CPU finished it's STARTUP sequence?
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*/
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if (cpu_isset(cpuid, cpu_callout_map))
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break;
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cpu_relax();
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}
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if (!time_before(jiffies, timeout)) {
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panic("smp_callin: CPU%d started up but did not get a callout!\n",
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cpuid);
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}
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/*
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* the boot CPU has finished the init stage and is spinning
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* on callin_map until we finish. We are free to set up this
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* CPU, first the APIC. (this is probably redundant on most
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* boards)
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*/
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Dprintk("CALLIN, before setup_local_APIC().\n");
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setup_local_APIC();
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/*
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* Get our bogomips.
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*
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* Need to enable IRQs because it can take longer and then
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* the NMI watchdog might kill us.
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*/
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local_irq_enable();
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calibrate_delay();
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local_irq_disable();
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Dprintk("Stack at about %p\n",&cpuid);
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disable_APIC_timer();
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/*
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* Save our processor parameters
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*/
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smp_store_cpu_info(cpuid);
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/*
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* Allow the master to continue.
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*/
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cpu_set(cpuid, cpu_callin_map);
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}
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static inline void set_cpu_sibling_map(int cpu)
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{
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int i;
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if (smp_num_siblings > 1) {
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for_each_cpu(i) {
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if (cpu_core_id[cpu] == cpu_core_id[i]) {
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cpu_set(i, cpu_sibling_map[cpu]);
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cpu_set(cpu, cpu_sibling_map[i]);
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}
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}
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} else {
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cpu_set(cpu, cpu_sibling_map[cpu]);
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}
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if (current_cpu_data.x86_num_cores > 1) {
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for_each_cpu(i) {
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if (phys_proc_id[cpu] == phys_proc_id[i]) {
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cpu_set(i, cpu_core_map[cpu]);
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cpu_set(cpu, cpu_core_map[i]);
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}
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}
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} else {
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cpu_core_map[cpu] = cpu_sibling_map[cpu];
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}
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}
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/*
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* Setup code on secondary processor (after comming out of the trampoline)
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*/
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void __cpuinit start_secondary(void)
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{
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/*
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* Dont put anything before smp_callin(), SMP
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* booting is too fragile that we want to limit the
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* things done here to the most necessary things.
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*/
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cpu_init();
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smp_callin();
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/* otherwise gcc will move up the smp_processor_id before the cpu_init */
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barrier();
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Dprintk("cpu %d: setting up apic clock\n", smp_processor_id());
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setup_secondary_APIC_clock();
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Dprintk("cpu %d: enabling apic timer\n", smp_processor_id());
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if (nmi_watchdog == NMI_IO_APIC) {
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disable_8259A_irq(0);
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enable_NMI_through_LVT0(NULL);
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enable_8259A_irq(0);
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}
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enable_APIC_timer();
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/*
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* The sibling maps must be set before turing the online map on for
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* this cpu
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*/
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set_cpu_sibling_map(smp_processor_id());
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/*
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* Wait for TSC sync to not schedule things before.
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* We still process interrupts, which could see an inconsistent
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* time in that window unfortunately.
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* Do this here because TSC sync has global unprotected state.
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*/
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tsc_sync_wait();
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/*
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* We need to hold call_lock, so there is no inconsistency
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* between the time smp_call_function() determines number of
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* IPI receipients, and the time when the determination is made
|
|
* for which cpus receive the IPI in genapic_flat.c. Holding this
|
|
* lock helps us to not include this cpu in a currently in progress
|
|
* smp_call_function().
|
|
*/
|
|
lock_ipi_call_lock();
|
|
|
|
/*
|
|
* Allow the master to continue.
|
|
*/
|
|
cpu_set(smp_processor_id(), cpu_online_map);
|
|
per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
|
|
unlock_ipi_call_lock();
|
|
|
|
cpu_idle();
|
|
}
|
|
|
|
extern volatile unsigned long init_rsp;
|
|
extern void (*initial_code)(void);
|
|
|
|
#ifdef APIC_DEBUG
|
|
static void inquire_remote_apic(int apicid)
|
|
{
|
|
unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
|
|
char *names[] = { "ID", "VERSION", "SPIV" };
|
|
int timeout, status;
|
|
|
|
printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
|
|
|
|
for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
|
|
printk("... APIC #%d %s: ", apicid, names[i]);
|
|
|
|
/*
|
|
* Wait for idle.
|
|
*/
|
|
apic_wait_icr_idle();
|
|
|
|
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
|
|
apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]);
|
|
|
|
timeout = 0;
|
|
do {
|
|
udelay(100);
|
|
status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
|
|
} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
|
|
|
|
switch (status) {
|
|
case APIC_ICR_RR_VALID:
|
|
status = apic_read(APIC_RRR);
|
|
printk("%08x\n", status);
|
|
break;
|
|
default:
|
|
printk("failed\n");
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Kick the secondary to wake up.
|
|
*/
|
|
static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
|
|
{
|
|
unsigned long send_status = 0, accept_status = 0;
|
|
int maxlvt, timeout, num_starts, j;
|
|
|
|
Dprintk("Asserting INIT.\n");
|
|
|
|
/*
|
|
* Turn INIT on target chip
|
|
*/
|
|
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
/*
|
|
* Send IPI
|
|
*/
|
|
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
|
|
| APIC_DM_INIT);
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
timeout = 0;
|
|
do {
|
|
Dprintk("+");
|
|
udelay(100);
|
|
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
|
|
} while (send_status && (timeout++ < 1000));
|
|
|
|
mdelay(10);
|
|
|
|
Dprintk("Deasserting INIT.\n");
|
|
|
|
/* Target chip */
|
|
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
/* Send IPI */
|
|
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
timeout = 0;
|
|
do {
|
|
Dprintk("+");
|
|
udelay(100);
|
|
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
|
|
} while (send_status && (timeout++ < 1000));
|
|
|
|
atomic_set(&init_deasserted, 1);
|
|
|
|
num_starts = 2;
|
|
|
|
/*
|
|
* Run STARTUP IPI loop.
|
|
*/
|
|
Dprintk("#startup loops: %d.\n", num_starts);
|
|
|
|
maxlvt = get_maxlvt();
|
|
|
|
for (j = 1; j <= num_starts; j++) {
|
|
Dprintk("Sending STARTUP #%d.\n",j);
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
Dprintk("After apic_write.\n");
|
|
|
|
/*
|
|
* STARTUP IPI
|
|
*/
|
|
|
|
/* Target chip */
|
|
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
|
|
|
|
/* Boot on the stack */
|
|
/* Kick the second */
|
|
apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12));
|
|
|
|
/*
|
|
* Give the other CPU some time to accept the IPI.
|
|
*/
|
|
udelay(300);
|
|
|
|
Dprintk("Startup point 1.\n");
|
|
|
|
Dprintk("Waiting for send to finish...\n");
|
|
timeout = 0;
|
|
do {
|
|
Dprintk("+");
|
|
udelay(100);
|
|
send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
|
|
} while (send_status && (timeout++ < 1000));
|
|
|
|
/*
|
|
* Give the other CPU some time to accept the IPI.
|
|
*/
|
|
udelay(200);
|
|
/*
|
|
* Due to the Pentium erratum 3AP.
|
|
*/
|
|
if (maxlvt > 3) {
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
}
|
|
accept_status = (apic_read(APIC_ESR) & 0xEF);
|
|
if (send_status || accept_status)
|
|
break;
|
|
}
|
|
Dprintk("After Startup.\n");
|
|
|
|
if (send_status)
|
|
printk(KERN_ERR "APIC never delivered???\n");
|
|
if (accept_status)
|
|
printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
|
|
|
|
return (send_status | accept_status);
|
|
}
|
|
|
|
struct create_idle {
|
|
struct task_struct *idle;
|
|
struct completion done;
|
|
int cpu;
|
|
};
|
|
|
|
void do_fork_idle(void *_c_idle)
|
|
{
|
|
struct create_idle *c_idle = _c_idle;
|
|
|
|
c_idle->idle = fork_idle(c_idle->cpu);
|
|
complete(&c_idle->done);
|
|
}
|
|
|
|
/*
|
|
* Boot one CPU.
|
|
*/
|
|
static int __cpuinit do_boot_cpu(int cpu, int apicid)
|
|
{
|
|
unsigned long boot_error;
|
|
int timeout;
|
|
unsigned long start_rip;
|
|
struct create_idle c_idle = {
|
|
.cpu = cpu,
|
|
.done = COMPLETION_INITIALIZER(c_idle.done),
|
|
};
|
|
DECLARE_WORK(work, do_fork_idle, &c_idle);
|
|
|
|
c_idle.idle = get_idle_for_cpu(cpu);
|
|
|
|
if (c_idle.idle) {
|
|
c_idle.idle->thread.rsp = (unsigned long) (((struct pt_regs *)
|
|
(THREAD_SIZE + (unsigned long) c_idle.idle->thread_info)) - 1);
|
|
init_idle(c_idle.idle, cpu);
|
|
goto do_rest;
|
|
}
|
|
|
|
/*
|
|
* During cold boot process, keventd thread is not spun up yet.
|
|
* When we do cpu hot-add, we create idle threads on the fly, we should
|
|
* not acquire any attributes from the calling context. Hence the clean
|
|
* way to create kernel_threads() is to do that from keventd().
|
|
* We do the current_is_keventd() due to the fact that ACPI notifier
|
|
* was also queuing to keventd() and when the caller is already running
|
|
* in context of keventd(), we would end up with locking up the keventd
|
|
* thread.
|
|
*/
|
|
if (!keventd_up() || current_is_keventd())
|
|
work.func(work.data);
|
|
else {
|
|
schedule_work(&work);
|
|
wait_for_completion(&c_idle.done);
|
|
}
|
|
|
|
if (IS_ERR(c_idle.idle)) {
|
|
printk("failed fork for CPU %d\n", cpu);
|
|
return PTR_ERR(c_idle.idle);
|
|
}
|
|
|
|
set_idle_for_cpu(cpu, c_idle.idle);
|
|
|
|
do_rest:
|
|
|
|
cpu_pda[cpu].pcurrent = c_idle.idle;
|
|
|
|
start_rip = setup_trampoline();
|
|
|
|
init_rsp = c_idle.idle->thread.rsp;
|
|
per_cpu(init_tss,cpu).rsp0 = init_rsp;
|
|
initial_code = start_secondary;
|
|
clear_ti_thread_flag(c_idle.idle->thread_info, TIF_FORK);
|
|
|
|
printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu,
|
|
cpus_weight(cpu_present_map),
|
|
apicid);
|
|
|
|
/*
|
|
* This grunge runs the startup process for
|
|
* the targeted processor.
|
|
*/
|
|
|
|
atomic_set(&init_deasserted, 0);
|
|
|
|
Dprintk("Setting warm reset code and vector.\n");
|
|
|
|
CMOS_WRITE(0xa, 0xf);
|
|
local_flush_tlb();
|
|
Dprintk("1.\n");
|
|
*((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
|
|
Dprintk("2.\n");
|
|
*((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
|
|
Dprintk("3.\n");
|
|
|
|
/*
|
|
* Be paranoid about clearing APIC errors.
|
|
*/
|
|
if (APIC_INTEGRATED(apic_version[apicid])) {
|
|
apic_read_around(APIC_SPIV);
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
}
|
|
|
|
/*
|
|
* Status is now clean
|
|
*/
|
|
boot_error = 0;
|
|
|
|
/*
|
|
* Starting actual IPI sequence...
|
|
*/
|
|
boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
|
|
|
|
if (!boot_error) {
|
|
/*
|
|
* allow APs to start initializing.
|
|
*/
|
|
Dprintk("Before Callout %d.\n", cpu);
|
|
cpu_set(cpu, cpu_callout_map);
|
|
Dprintk("After Callout %d.\n", cpu);
|
|
|
|
/*
|
|
* Wait 5s total for a response
|
|
*/
|
|
for (timeout = 0; timeout < 50000; timeout++) {
|
|
if (cpu_isset(cpu, cpu_callin_map))
|
|
break; /* It has booted */
|
|
udelay(100);
|
|
}
|
|
|
|
if (cpu_isset(cpu, cpu_callin_map)) {
|
|
/* number CPUs logically, starting from 1 (BSP is 0) */
|
|
Dprintk("CPU has booted.\n");
|
|
} else {
|
|
boot_error = 1;
|
|
if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
|
|
== 0xA5)
|
|
/* trampoline started but...? */
|
|
printk("Stuck ??\n");
|
|
else
|
|
/* trampoline code not run */
|
|
printk("Not responding.\n");
|
|
#ifdef APIC_DEBUG
|
|
inquire_remote_apic(apicid);
|
|
#endif
|
|
}
|
|
}
|
|
if (boot_error) {
|
|
cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
|
|
clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
|
|
cpu_clear(cpu, cpu_present_map);
|
|
cpu_clear(cpu, cpu_possible_map);
|
|
x86_cpu_to_apicid[cpu] = BAD_APICID;
|
|
x86_cpu_to_log_apicid[cpu] = BAD_APICID;
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
cycles_t cacheflush_time;
|
|
unsigned long cache_decay_ticks;
|
|
|
|
/*
|
|
* Cleanup possible dangling ends...
|
|
*/
|
|
static __cpuinit void smp_cleanup_boot(void)
|
|
{
|
|
/*
|
|
* Paranoid: Set warm reset code and vector here back
|
|
* to default values.
|
|
*/
|
|
CMOS_WRITE(0, 0xf);
|
|
|
|
/*
|
|
* Reset trampoline flag
|
|
*/
|
|
*((volatile int *) phys_to_virt(0x467)) = 0;
|
|
}
|
|
|
|
/*
|
|
* Fall back to non SMP mode after errors.
|
|
*
|
|
* RED-PEN audit/test this more. I bet there is more state messed up here.
|
|
*/
|
|
static __init void disable_smp(void)
|
|
{
|
|
cpu_present_map = cpumask_of_cpu(0);
|
|
cpu_possible_map = cpumask_of_cpu(0);
|
|
if (smp_found_config)
|
|
phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
|
|
else
|
|
phys_cpu_present_map = physid_mask_of_physid(0);
|
|
cpu_set(0, cpu_sibling_map[0]);
|
|
cpu_set(0, cpu_core_map[0]);
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
/*
|
|
* cpu_possible_map should be static, it cannot change as cpu's
|
|
* are onlined, or offlined. The reason is per-cpu data-structures
|
|
* are allocated by some modules at init time, and dont expect to
|
|
* do this dynamically on cpu arrival/departure.
|
|
* cpu_present_map on the other hand can change dynamically.
|
|
* In case when cpu_hotplug is not compiled, then we resort to current
|
|
* behaviour, which is cpu_possible == cpu_present.
|
|
* If cpu-hotplug is supported, then we need to preallocate for all
|
|
* those NR_CPUS, hence cpu_possible_map represents entire NR_CPUS range.
|
|
* - Ashok Raj
|
|
*/
|
|
__init void prefill_possible_map(void)
|
|
{
|
|
int i;
|
|
for (i = 0; i < NR_CPUS; i++)
|
|
cpu_set(i, cpu_possible_map);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Various sanity checks.
|
|
*/
|
|
static int __init smp_sanity_check(unsigned max_cpus)
|
|
{
|
|
if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
|
|
printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
|
|
hard_smp_processor_id());
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
}
|
|
|
|
/*
|
|
* If we couldn't find an SMP configuration at boot time,
|
|
* get out of here now!
|
|
*/
|
|
if (!smp_found_config) {
|
|
printk(KERN_NOTICE "SMP motherboard not detected.\n");
|
|
disable_smp();
|
|
if (APIC_init_uniprocessor())
|
|
printk(KERN_NOTICE "Local APIC not detected."
|
|
" Using dummy APIC emulation.\n");
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Should not be necessary because the MP table should list the boot
|
|
* CPU too, but we do it for the sake of robustness anyway.
|
|
*/
|
|
if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
|
|
printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
|
|
boot_cpu_id);
|
|
physid_set(hard_smp_processor_id(), phys_cpu_present_map);
|
|
}
|
|
|
|
/*
|
|
* If we couldn't find a local APIC, then get out of here now!
|
|
*/
|
|
if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
|
|
printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
|
|
boot_cpu_id);
|
|
printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
|
|
nr_ioapics = 0;
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* If SMP should be disabled, then really disable it!
|
|
*/
|
|
if (!max_cpus) {
|
|
printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
|
|
nr_ioapics = 0;
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Prepare for SMP bootup. The MP table or ACPI has been read
|
|
* earlier. Just do some sanity checking here and enable APIC mode.
|
|
*/
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
nmi_watchdog_default();
|
|
current_cpu_data = boot_cpu_data;
|
|
current_thread_info()->cpu = 0; /* needed? */
|
|
|
|
if (smp_sanity_check(max_cpus) < 0) {
|
|
printk(KERN_INFO "SMP disabled\n");
|
|
disable_smp();
|
|
return;
|
|
}
|
|
|
|
|
|
/*
|
|
* Switch from PIC to APIC mode.
|
|
*/
|
|
connect_bsp_APIC();
|
|
setup_local_APIC();
|
|
|
|
if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) {
|
|
panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
|
|
GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id);
|
|
/* Or can we switch back to PIC here? */
|
|
}
|
|
|
|
/*
|
|
* Now start the IO-APICs
|
|
*/
|
|
if (!skip_ioapic_setup && nr_ioapics)
|
|
setup_IO_APIC();
|
|
else
|
|
nr_ioapics = 0;
|
|
|
|
/*
|
|
* Set up local APIC timer on boot CPU.
|
|
*/
|
|
|
|
setup_boot_APIC_clock();
|
|
}
|
|
|
|
/*
|
|
* Early setup to make printk work.
|
|
*/
|
|
void __init smp_prepare_boot_cpu(void)
|
|
{
|
|
int me = smp_processor_id();
|
|
cpu_set(me, cpu_online_map);
|
|
cpu_set(me, cpu_callout_map);
|
|
cpu_set(0, cpu_sibling_map[0]);
|
|
cpu_set(0, cpu_core_map[0]);
|
|
per_cpu(cpu_state, me) = CPU_ONLINE;
|
|
}
|
|
|
|
/*
|
|
* Entry point to boot a CPU.
|
|
*/
|
|
int __cpuinit __cpu_up(unsigned int cpu)
|
|
{
|
|
int err;
|
|
int apicid = cpu_present_to_apicid(cpu);
|
|
|
|
WARN_ON(irqs_disabled());
|
|
|
|
Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu);
|
|
|
|
if (apicid == BAD_APICID || apicid == boot_cpu_id ||
|
|
!physid_isset(apicid, phys_cpu_present_map)) {
|
|
printk("__cpu_up: bad cpu %d\n", cpu);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Already booted CPU?
|
|
*/
|
|
if (cpu_isset(cpu, cpu_callin_map)) {
|
|
Dprintk("do_boot_cpu %d Already started\n", cpu);
|
|
return -ENOSYS;
|
|
}
|
|
|
|
per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
|
|
/* Boot it! */
|
|
err = do_boot_cpu(cpu, apicid);
|
|
if (err < 0) {
|
|
Dprintk("do_boot_cpu failed %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
/* Unleash the CPU! */
|
|
Dprintk("waiting for cpu %d\n", cpu);
|
|
|
|
while (!cpu_isset(cpu, cpu_online_map))
|
|
cpu_relax();
|
|
err = 0;
|
|
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* Finish the SMP boot.
|
|
*/
|
|
void __init smp_cpus_done(unsigned int max_cpus)
|
|
{
|
|
smp_cleanup_boot();
|
|
|
|
#ifdef CONFIG_X86_IO_APIC
|
|
setup_ioapic_dest();
|
|
#endif
|
|
|
|
time_init_gtod();
|
|
|
|
check_nmi_watchdog();
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
static void remove_siblinginfo(int cpu)
|
|
{
|
|
int sibling;
|
|
|
|
for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
|
|
cpu_clear(cpu, cpu_sibling_map[sibling]);
|
|
for_each_cpu_mask(sibling, cpu_core_map[cpu])
|
|
cpu_clear(cpu, cpu_core_map[sibling]);
|
|
cpus_clear(cpu_sibling_map[cpu]);
|
|
cpus_clear(cpu_core_map[cpu]);
|
|
phys_proc_id[cpu] = BAD_APICID;
|
|
cpu_core_id[cpu] = BAD_APICID;
|
|
}
|
|
|
|
void remove_cpu_from_maps(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
cpu_clear(cpu, cpu_callout_map);
|
|
cpu_clear(cpu, cpu_callin_map);
|
|
clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
|
|
}
|
|
|
|
int __cpu_disable(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
/*
|
|
* Perhaps use cpufreq to drop frequency, but that could go
|
|
* into generic code.
|
|
*
|
|
* We won't take down the boot processor on i386 due to some
|
|
* interrupts only being able to be serviced by the BSP.
|
|
* Especially so if we're not using an IOAPIC -zwane
|
|
*/
|
|
if (cpu == 0)
|
|
return -EBUSY;
|
|
|
|
disable_APIC_timer();
|
|
|
|
/*
|
|
* HACK:
|
|
* Allow any queued timer interrupts to get serviced
|
|
* This is only a temporary solution until we cleanup
|
|
* fixup_irqs as we do for IA64.
|
|
*/
|
|
local_irq_enable();
|
|
mdelay(1);
|
|
|
|
local_irq_disable();
|
|
remove_siblinginfo(cpu);
|
|
|
|
/* It's now safe to remove this processor from the online map */
|
|
cpu_clear(cpu, cpu_online_map);
|
|
remove_cpu_from_maps();
|
|
fixup_irqs(cpu_online_map);
|
|
return 0;
|
|
}
|
|
|
|
void __cpu_die(unsigned int cpu)
|
|
{
|
|
/* We don't do anything here: idle task is faking death itself. */
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
/* They ack this in play_dead by setting CPU_DEAD */
|
|
if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
|
|
printk ("CPU %d is now offline\n", cpu);
|
|
return;
|
|
}
|
|
msleep(100);
|
|
}
|
|
printk(KERN_ERR "CPU %u didn't die...\n", cpu);
|
|
}
|
|
|
|
#else /* ... !CONFIG_HOTPLUG_CPU */
|
|
|
|
int __cpu_disable(void)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
void __cpu_die(unsigned int cpu)
|
|
{
|
|
/* We said "no" in __cpu_disable */
|
|
BUG();
|
|
}
|
|
#endif /* CONFIG_HOTPLUG_CPU */
|