mirror of https://gitee.com/openkylin/linux.git
161 lines
3.1 KiB
Plaintext
161 lines
3.1 KiB
Plaintext
/*
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* Copyright 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &r_uart;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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memory {
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reg = <0x40000000 0x40000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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timer@01c20c00 {
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compatible = "allwinner,sun4i-a10-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <0 18 4>,
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<0 19 4>;
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clocks = <&osc24M>;
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};
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wdt0: watchdog@01c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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interrupts = <0 25 4>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <0 0 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <0 1 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <0 2 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <0 3 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart4: serial@01c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <0 4 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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gic: interrupt-controller@01c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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<0x01c82000 0x1000>,
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<0x01c84000 0x2000>,
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<0x01c86000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <1 9 0xf04>;
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};
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r_uart: serial@01f02800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01f02800 0x400>;
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interrupts = <0 38 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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};
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};
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