mirror of https://gitee.com/openkylin/linux.git
796 lines
19 KiB
Plaintext
796 lines
19 KiB
Plaintext
/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Based on "omap4.dtsi"
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/dra.h>
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#include "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ti,dra7xx";
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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i2c4 = &i2c5;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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operating-points = <
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/* kHz uV */
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1000000 1060000
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1176000 1160000
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>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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gic: interrupt-controller@48211000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48211000 0x1000>,
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<0x48212000 0x1000>,
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<0x48214000 0x2000>,
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<0x48216000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu";
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};
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};
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/*
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* XXX: Use a flat representation of the SOC interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since it will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "ti,omap4-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main_1", "l3_main_2";
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reg = <0x44000000 0x2000>,
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<0x44800000 0x3000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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prm: prm@4ae06000 {
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compatible = "ti,dra7-prm";
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reg = <0x4ae06000 0x3000>;
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prm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prm_clockdomains: clockdomains {
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};
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};
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cm_core_aon: cm_core_aon@4a005000 {
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compatible = "ti,dra7-cm-core-aon";
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reg = <0x4a005000 0x2000>;
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cm_core_aon_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_aon_clockdomains: clockdomains {
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};
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};
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cm_core: cm_core@4a008000 {
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compatible = "ti,dra7-cm-core";
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reg = <0x4a008000 0x3000>;
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cm_core_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_clockdomains: clockdomains {
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};
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};
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counter32k: counter@4ae04000 {
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compatible = "ti,omap-counter32k";
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reg = <0x4ae04000 0x40>;
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ti,hwmods = "counter_32k";
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};
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dra7_ctrl_general: tisyscon@4a002e00 {
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compatible = "syscon";
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reg = <0x4a002e00 0x7c>;
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};
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pbias_regulator: pbias_regulator {
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compatible = "ti,pbias-omap";
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reg = <0 0x4>;
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syscon = <&dra7_ctrl_general>;
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pbias_mmc_reg: pbias_mmc_omap5 {
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regulator-name = "pbias_mmc_omap5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3000000>;
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};
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};
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dra7_pmx_core: pinmux@4a003400 {
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compatible = "pinctrl-single";
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reg = <0x4a003400 0x0464>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x3fffffff>;
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};
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sdma: dma-controller@4a056000 {
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compatible = "ti,omap4430-sdma";
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reg = <0x4a056000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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#dma-channels = <32>;
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#dma-requests = <127>;
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};
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gpio1: gpio@4ae10000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4ae10000 0x200>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio1";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio2: gpio@48055000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48055000 0x200>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio2";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio3: gpio@48057000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48057000 0x200>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio3";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio4: gpio@48059000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48059000 0x200>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio4";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio5: gpio@4805b000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4805b000 0x200>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio5";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio6: gpio@4805d000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4805d000 0x200>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio6";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio7: gpio@48051000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48051000 0x200>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio7";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio8: gpio@48053000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48053000 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio8";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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uart1: serial@4806a000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart1";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart2: serial@4806c000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806c000 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart2";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart3: serial@48020000 {
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compatible = "ti,omap4-uart";
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reg = <0x48020000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart3";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart4: serial@4806e000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806e000 0x100>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart4";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart5: serial@48066000 {
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compatible = "ti,omap4-uart";
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reg = <0x48066000 0x100>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart5";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart6: serial@48068000 {
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compatible = "ti,omap4-uart";
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reg = <0x48068000 0x100>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart6";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart7: serial@48420000 {
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compatible = "ti,omap4-uart";
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reg = <0x48420000 0x100>;
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ti,hwmods = "uart7";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart8: serial@48422000 {
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compatible = "ti,omap4-uart";
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reg = <0x48422000 0x100>;
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ti,hwmods = "uart8";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart9: serial@48424000 {
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compatible = "ti,omap4-uart";
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reg = <0x48424000 0x100>;
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ti,hwmods = "uart9";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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uart10: serial@4ae2b000 {
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compatible = "ti,omap4-uart";
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reg = <0x4ae2b000 0x100>;
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ti,hwmods = "uart10";
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clock-frequency = <48000000>;
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status = "disabled";
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};
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timer1: timer@4ae18000 {
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compatible = "ti,omap5430-timer";
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reg = <0x4ae18000 0x80>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer1";
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ti,timer-alwon;
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};
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timer2: timer@48032000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48032000 0x80>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer2";
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};
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timer3: timer@48034000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48034000 0x80>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer3";
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};
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timer4: timer@48036000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48036000 0x80>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer4";
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};
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timer5: timer@48820000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48820000 0x80>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer5";
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ti,timer-dsp;
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};
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timer6: timer@48822000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48822000 0x80>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer6";
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ti,timer-dsp;
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ti,timer-pwm;
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};
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timer7: timer@48824000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48824000 0x80>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer7";
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ti,timer-dsp;
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};
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timer8: timer@48826000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48826000 0x80>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer8";
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ti,timer-dsp;
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ti,timer-pwm;
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};
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timer9: timer@4803e000 {
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compatible = "ti,omap5430-timer";
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reg = <0x4803e000 0x80>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer9";
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};
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timer10: timer@48086000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48086000 0x80>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer10";
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};
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timer11: timer@48088000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48088000 0x80>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer11";
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ti,timer-pwm;
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};
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timer13: timer@48828000 {
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compatible = "ti,omap5430-timer";
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reg = <0x48828000 0x80>;
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ti,hwmods = "timer13";
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status = "disabled";
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};
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timer14: timer@4882a000 {
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compatible = "ti,omap5430-timer";
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reg = <0x4882a000 0x80>;
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ti,hwmods = "timer14";
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status = "disabled";
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};
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timer15: timer@4882c000 {
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compatible = "ti,omap5430-timer";
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reg = <0x4882c000 0x80>;
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ti,hwmods = "timer15";
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status = "disabled";
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};
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timer16: timer@4882e000 {
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compatible = "ti,omap5430-timer";
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reg = <0x4882e000 0x80>;
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ti,hwmods = "timer16";
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status = "disabled";
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};
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wdt2: wdt@4ae14000 {
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compatible = "ti,omap4-wdt";
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reg = <0x4ae14000 0x80>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "wd_timer2";
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};
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hwspinlock: spinlock@4a0f6000 {
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compatible = "ti,omap4-hwspinlock";
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reg = <0x4a0f6000 0x1000>;
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ti,hwmods = "spinlock";
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#hwlock-cells = <1>;
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};
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dmm@4e000000 {
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compatible = "ti,omap5-dmm";
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reg = <0x4e000000 0x800>;
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interrupts = <0 113 0x4>;
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ti,hwmods = "dmm";
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};
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i2c1: i2c@48070000 {
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compatible = "ti,omap4-i2c";
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reg = <0x48070000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c1";
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status = "disabled";
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};
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i2c2: i2c@48072000 {
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compatible = "ti,omap4-i2c";
|
|
reg = <0x48072000 0x100>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c2";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@48060000 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x48060000 0x100>;
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c3";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@4807a000 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x4807a000 0x100>;
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c4";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@4807c000 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x4807c000 0x100>;
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "i2c5";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@4809c000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x4809c000 0x400>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc1";
|
|
ti,dual-volt;
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 61>, <&sdma 62>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
pbias-supply = <&pbias_mmc_reg>;
|
|
};
|
|
|
|
mmc2: mmc@480b4000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480b4000 0x400>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc2";
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 47>, <&sdma 48>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc3: mmc@480ad000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480ad000 0x400>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc3";
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 77>, <&sdma 78>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc4: mmc@480d1000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480d1000 0x400>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc4";
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 57>, <&sdma 58>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
abb_mpu: regulator-abb-mpu {
|
|
compatible = "ti,abb-v3";
|
|
regulator-name = "abb_mpu";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin1>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
|
|
<0x4ae06014 0x4>, <0x4a003b20 0x8>,
|
|
<0x4ae0c158 0x4>;
|
|
reg-names = "setup-address", "control-address",
|
|
"int-address", "efuse-address",
|
|
"ldo-address";
|
|
ti,tranxdone-status-mask = <0x80>;
|
|
/* LDOVBBMPU_FBB_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBMPU_FBB_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1060000 0 0x0 0 0x02000000 0x01F00000
|
|
1160000 0 0x4 0 0x02000000 0x01F00000
|
|
1210000 0 0x8 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
abb_ivahd: regulator-abb-ivahd {
|
|
compatible = "ti,abb-v3";
|
|
regulator-name = "abb_ivahd";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin1>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
|
|
<0x4ae06010 0x4>, <0x4a0025cc 0x8>,
|
|
<0x4a002470 0x4>;
|
|
reg-names = "setup-address", "control-address",
|
|
"int-address", "efuse-address",
|
|
"ldo-address";
|
|
ti,tranxdone-status-mask = <0x40000000>;
|
|
/* LDOVBBIVA_FBB_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBIVA_FBB_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1055000 0 0x0 0 0x02000000 0x01F00000
|
|
1150000 0 0x4 0 0x02000000 0x01F00000
|
|
1250000 0 0x8 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
abb_dspeve: regulator-abb-dspeve {
|
|
compatible = "ti,abb-v3";
|
|
regulator-name = "abb_dspeve";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin1>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
|
|
<0x4ae06010 0x4>, <0x4a0025e0 0x8>,
|
|
<0x4a00246c 0x4>;
|
|
reg-names = "setup-address", "control-address",
|
|
"int-address", "efuse-address",
|
|
"ldo-address";
|
|
ti,tranxdone-status-mask = <0x20000000>;
|
|
/* LDOVBBDSPEVE_FBB_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBDSPEVE_FBB_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1055000 0 0x0 0 0x02000000 0x01F00000
|
|
1150000 0 0x4 0 0x02000000 0x01F00000
|
|
1250000 0 0x8 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
abb_gpu: regulator-abb-gpu {
|
|
compatible = "ti,abb-v3";
|
|
regulator-name = "abb_gpu";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin1>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
|
|
<0x4ae06010 0x4>, <0x4a003b08 0x8>,
|
|
<0x4ae0c154 0x4>;
|
|
reg-names = "setup-address", "control-address",
|
|
"int-address", "efuse-address",
|
|
"ldo-address";
|
|
ti,tranxdone-status-mask = <0x10000000>;
|
|
/* LDOVBBGPU_FBB_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBGPU_FBB_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1090000 0 0x0 0 0x02000000 0x01F00000
|
|
1210000 0 0x4 0 0x02000000 0x01F00000
|
|
1280000 0 0x8 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
mcspi1: spi@48098000 {
|
|
compatible = "ti,omap4-mcspi";
|
|
reg = <0x48098000 0x200>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "mcspi1";
|
|
ti,spi-num-cs = <4>;
|
|
dmas = <&sdma 35>,
|
|
<&sdma 36>,
|
|
<&sdma 37>,
|
|
<&sdma 38>,
|
|
<&sdma 39>,
|
|
<&sdma 40>,
|
|
<&sdma 41>,
|
|
<&sdma 42>;
|
|
dma-names = "tx0", "rx0", "tx1", "rx1",
|
|
"tx2", "rx2", "tx3", "rx3";
|
|
status = "disabled";
|
|
};
|
|
|
|
mcspi2: spi@4809a000 {
|
|
compatible = "ti,omap4-mcspi";
|
|
reg = <0x4809a000 0x200>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "mcspi2";
|
|
ti,spi-num-cs = <2>;
|
|
dmas = <&sdma 43>,
|
|
<&sdma 44>,
|
|
<&sdma 45>,
|
|
<&sdma 46>;
|
|
dma-names = "tx0", "rx0", "tx1", "rx1";
|
|
status = "disabled";
|
|
};
|
|
|
|
mcspi3: spi@480b8000 {
|
|
compatible = "ti,omap4-mcspi";
|
|
reg = <0x480b8000 0x200>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "mcspi3";
|
|
ti,spi-num-cs = <2>;
|
|
dmas = <&sdma 15>, <&sdma 16>;
|
|
dma-names = "tx0", "rx0";
|
|
status = "disabled";
|
|
};
|
|
|
|
mcspi4: spi@480ba000 {
|
|
compatible = "ti,omap4-mcspi";
|
|
reg = <0x480ba000 0x200>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "mcspi4";
|
|
ti,spi-num-cs = <1>;
|
|
dmas = <&sdma 70>, <&sdma 71>;
|
|
dma-names = "tx0", "rx0";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
/include/ "dra7xx-clocks.dtsi"
|