mirror of https://gitee.com/openkylin/linux.git
670 lines
17 KiB
C
670 lines
17 KiB
C
/*
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* Performance counter support for POWER8 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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* Copyright 2013 Michael Ellerman, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#define pr_fmt(fmt) "power8-pmu: " fmt
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#include "isa207-common.h"
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/*
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* Some power8 event codes.
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*/
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#define EVENT(_name, _code) _name = _code,
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enum {
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#include "power8-events-list.h"
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};
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#undef EVENT
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/* MMCRA IFM bits - POWER8 */
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#define POWER8_MMCRA_IFM1 0x0000000040000000UL
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#define POWER8_MMCRA_IFM2 0x0000000080000000UL
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#define POWER8_MMCRA_IFM3 0x00000000C0000000UL
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static inline bool event_is_fab_match(u64 event)
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{
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/* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
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event &= 0xff0fe;
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/* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
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return (event == 0x30056 || event == 0x4f052);
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}
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static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
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{
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unsigned int unit, pmc, cache, ebb;
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unsigned long mask, value;
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mask = value = 0;
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if (event & ~EVENT_VALID_MASK)
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return -1;
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pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
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cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
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ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
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if (pmc) {
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u64 base_event;
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if (pmc > 6)
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return -1;
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/* Ignore Linux defined bits when checking event below */
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base_event = event & ~EVENT_LINUX_MASK;
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if (pmc >= 5 && base_event != PM_RUN_INST_CMPL &&
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base_event != PM_RUN_CYC)
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return -1;
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mask |= CNST_PMC_MASK(pmc);
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value |= CNST_PMC_VAL(pmc);
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}
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if (pmc <= 4) {
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/*
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* Add to number of counters in use. Note this includes events with
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* a PMC of 0 - they still need a PMC, it's just assigned later.
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* Don't count events on PMC 5 & 6, there is only one valid event
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* on each of those counters, and they are handled above.
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*/
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mask |= CNST_NC_MASK;
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value |= CNST_NC_VAL;
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}
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if (unit >= 6 && unit <= 9) {
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/*
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* L2/L3 events contain a cache selector field, which is
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* supposed to be programmed into MMCRC. However MMCRC is only
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* HV writable, and there is no API for guest kernels to modify
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* it. The solution is for the hypervisor to initialise the
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* field to zeroes, and for us to only ever allow events that
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* have a cache selector of zero. The bank selector (bit 3) is
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* irrelevant, as long as the rest of the value is 0.
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*/
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if (cache & 0x7)
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return -1;
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} else if (event & EVENT_IS_L1) {
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mask |= CNST_L1_QUAL_MASK;
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value |= CNST_L1_QUAL_VAL(cache);
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}
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if (event & EVENT_IS_MARKED) {
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mask |= CNST_SAMPLE_MASK;
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value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
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}
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/*
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* Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
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* the threshold control bits are used for the match value.
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*/
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if (event_is_fab_match(event)) {
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mask |= CNST_FAB_MATCH_MASK;
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value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
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} else {
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/*
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* Check the mantissa upper two bits are not zero, unless the
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* exponent is also zero. See the THRESH_CMP_MANTISSA doc.
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*/
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unsigned int cmp, exp;
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cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
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exp = cmp >> 7;
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if (exp && (cmp & 0x60) == 0)
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return -1;
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mask |= CNST_THRESH_MASK;
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value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
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}
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if (!pmc && ebb)
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/* EBB events must specify the PMC */
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return -1;
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if (event & EVENT_WANTS_BHRB) {
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if (!ebb)
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/* Only EBB events can request BHRB */
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return -1;
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mask |= CNST_IFM_MASK;
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value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
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}
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/*
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* All events must agree on EBB, either all request it or none.
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* EBB events are pinned & exclusive, so this should never actually
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* hit, but we leave it as a fallback in case.
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*/
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mask |= CNST_EBB_VAL(ebb);
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value |= CNST_EBB_MASK;
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*maskp = mask;
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*valp = value;
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return 0;
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}
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static int power8_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[],
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struct perf_event *pevents[])
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{
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unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
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unsigned int pmc, pmc_inuse;
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int i;
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pmc_inuse = 0;
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/* First pass to count resource use */
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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if (pmc)
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pmc_inuse |= 1 << pmc;
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}
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/* In continuous sampling mode, update SDAR on TLB miss */
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mmcra = MMCRA_SDAR_MODE_TLB;
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mmcr1 = mmcr2 = 0;
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/* Second pass: assign PMCs, set all MMCR1 fields */
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
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combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
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psel = event[i] & EVENT_PSEL_MASK;
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if (!pmc) {
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for (pmc = 1; pmc <= 4; ++pmc) {
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if (!(pmc_inuse & (1 << pmc)))
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break;
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}
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pmc_inuse |= 1 << pmc;
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}
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if (pmc <= 4) {
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mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
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mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc);
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mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
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}
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if (event[i] & EVENT_IS_L1) {
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cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
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mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
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cache >>= 1;
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mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
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}
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if (event[i] & EVENT_IS_MARKED) {
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mmcra |= MMCRA_SAMPLE_ENABLE;
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val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
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if (val) {
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mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
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mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
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}
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}
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/*
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* PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
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* the threshold bits are used for the match value.
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*/
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if (event_is_fab_match(event[i])) {
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mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
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EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
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} else {
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val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
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mmcra |= val << MMCRA_THR_CTL_SHIFT;
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val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
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mmcra |= val << MMCRA_THR_SEL_SHIFT;
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val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
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mmcra |= val << MMCRA_THR_CMP_SHIFT;
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}
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if (event[i] & EVENT_WANTS_BHRB) {
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val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
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mmcra |= val << MMCRA_IFM_SHIFT;
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}
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if (pevents[i]->attr.exclude_user)
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mmcr2 |= MMCR2_FCP(pmc);
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if (pevents[i]->attr.exclude_hv)
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mmcr2 |= MMCR2_FCH(pmc);
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if (pevents[i]->attr.exclude_kernel) {
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if (cpu_has_feature(CPU_FTR_HVMODE))
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mmcr2 |= MMCR2_FCH(pmc);
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else
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mmcr2 |= MMCR2_FCS(pmc);
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}
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hwc[i] = pmc - 1;
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}
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/* Return MMCRx values */
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mmcr[0] = 0;
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/* pmc_inuse is 1-based */
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if (pmc_inuse & 2)
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mmcr[0] = MMCR0_PMC1CE;
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if (pmc_inuse & 0x7c)
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mmcr[0] |= MMCR0_PMCjCE;
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/* If we're not using PMC 5 or 6, freeze them */
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if (!(pmc_inuse & 0x60))
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mmcr[0] |= MMCR0_FC56;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcra;
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mmcr[3] = mmcr2;
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return 0;
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}
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/* Table of alternatives, sorted by column 0 */
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ PM_MRK_ST_CMPL, PM_MRK_ST_CMPL_ALT },
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{ PM_BR_MRK_2PATH, PM_BR_MRK_2PATH_ALT },
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{ PM_L3_CO_MEPF, PM_L3_CO_MEPF_ALT },
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{ PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L2MISS_ALT },
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{ PM_CMPLU_STALL_ALT, PM_CMPLU_STALL },
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{ PM_BR_2PATH, PM_BR_2PATH_ALT },
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{ PM_INST_DISP, PM_INST_DISP_ALT },
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{ PM_RUN_CYC_ALT, PM_RUN_CYC },
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{ PM_MRK_FILT_MATCH, PM_MRK_FILT_MATCH_ALT },
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{ PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
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{ PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
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};
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/*
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* Scan the alternatives table for a match and return the
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* index into the alternatives table if found, else -1.
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*/
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static int find_alternative(u64 event)
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{
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int i, j;
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for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
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if (event < event_alternatives[i][0])
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break;
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for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
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if (event == event_alternatives[i][j])
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return i;
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}
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return -1;
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}
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static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int i, j, num_alt = 0;
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u64 alt_event;
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alt[num_alt++] = event;
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i = find_alternative(event);
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if (i >= 0) {
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/* Filter out the original event, it's already in alt[0] */
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for (j = 0; j < MAX_ALT; ++j) {
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alt_event = event_alternatives[i][j];
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if (alt_event && alt_event != event)
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alt[num_alt++] = alt_event;
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}
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}
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if (flags & PPMU_ONLY_COUNT_RUN) {
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/*
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* We're only counting in RUN state, so PM_CYC is equivalent to
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* PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
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*/
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j = num_alt;
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for (i = 0; i < num_alt; ++i) {
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switch (alt[i]) {
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case PM_CYC:
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alt[j++] = PM_RUN_CYC;
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break;
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case PM_RUN_CYC:
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alt[j++] = PM_CYC;
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break;
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case PM_INST_CMPL:
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alt[j++] = PM_RUN_INST_CMPL;
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break;
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case PM_RUN_INST_CMPL:
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alt[j++] = PM_INST_CMPL;
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break;
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}
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}
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num_alt = j;
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}
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return num_alt;
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}
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static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[])
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{
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if (pmc <= 3)
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mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
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}
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GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
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GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC);
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GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
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GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
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GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
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GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
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GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
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GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
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CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
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CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
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CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
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CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
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CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
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CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
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CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
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CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
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CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
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CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
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CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
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CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
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CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN);
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CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
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CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
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static struct attribute *power8_events_attr[] = {
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GENERIC_EVENT_PTR(PM_CYC),
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GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
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GENERIC_EVENT_PTR(PM_CMPLU_STALL),
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GENERIC_EVENT_PTR(PM_INST_CMPL),
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GENERIC_EVENT_PTR(PM_BRU_FIN),
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GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
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GENERIC_EVENT_PTR(PM_LD_REF_L1),
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GENERIC_EVENT_PTR(PM_LD_MISS_L1),
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CACHE_EVENT_PTR(PM_LD_MISS_L1),
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CACHE_EVENT_PTR(PM_LD_REF_L1),
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CACHE_EVENT_PTR(PM_L1_PREF),
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CACHE_EVENT_PTR(PM_ST_MISS_L1),
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CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
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CACHE_EVENT_PTR(PM_INST_FROM_L1),
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CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3),
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CACHE_EVENT_PTR(PM_L3_PREF_ALL),
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CACHE_EVENT_PTR(PM_L2_ST_MISS),
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CACHE_EVENT_PTR(PM_L2_ST),
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CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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CACHE_EVENT_PTR(PM_BRU_FIN),
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CACHE_EVENT_PTR(PM_DTLB_MISS),
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CACHE_EVENT_PTR(PM_ITLB_MISS),
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NULL
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};
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static struct attribute_group power8_pmu_events_group = {
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.name = "events",
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.attrs = power8_events_attr,
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};
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PMU_FORMAT_ATTR(event, "config:0-49");
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
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PMU_FORMAT_ATTR(mark, "config:8");
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PMU_FORMAT_ATTR(combine, "config:11");
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PMU_FORMAT_ATTR(unit, "config:12-15");
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PMU_FORMAT_ATTR(pmc, "config:16-19");
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PMU_FORMAT_ATTR(cache_sel, "config:20-23");
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PMU_FORMAT_ATTR(sample_mode, "config:24-28");
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PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
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PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
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PMU_FORMAT_ATTR(thresh_start, "config:36-39");
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PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
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static struct attribute *power8_pmu_format_attr[] = {
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&format_attr_event.attr,
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&format_attr_pmcxsel.attr,
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&format_attr_mark.attr,
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&format_attr_combine.attr,
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&format_attr_unit.attr,
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&format_attr_pmc.attr,
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&format_attr_cache_sel.attr,
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&format_attr_sample_mode.attr,
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&format_attr_thresh_sel.attr,
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&format_attr_thresh_stop.attr,
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&format_attr_thresh_start.attr,
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&format_attr_thresh_cmp.attr,
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NULL,
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};
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struct attribute_group power8_pmu_format_group = {
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.name = "format",
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.attrs = power8_pmu_format_attr,
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};
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static const struct attribute_group *power8_pmu_attr_groups[] = {
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&power8_pmu_format_group,
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&power8_pmu_events_group,
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NULL,
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};
|
|
|
|
static int power8_generic_events[] = {
|
|
[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
|
|
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
|
|
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
|
|
[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
|
|
};
|
|
|
|
static u64 power8_bhrb_filter_map(u64 branch_sample_type)
|
|
{
|
|
u64 pmu_bhrb_filter = 0;
|
|
|
|
/* BHRB and regular PMU events share the same privilege state
|
|
* filter configuration. BHRB is always recorded along with a
|
|
* regular PMU event. As the privilege state filter is handled
|
|
* in the basic PMC configuration of the accompanying regular
|
|
* PMU event, we ignore any separate BHRB specific request.
|
|
*/
|
|
|
|
/* No branch filter requested */
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
|
|
return pmu_bhrb_filter;
|
|
|
|
/* Invalid branch filter options - HW does not support */
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
|
|
return -1;
|
|
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
|
|
return -1;
|
|
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
|
|
return -1;
|
|
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
|
|
pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
|
|
return pmu_bhrb_filter;
|
|
}
|
|
|
|
/* Every thing else is unsupported */
|
|
return -1;
|
|
}
|
|
|
|
static void power8_config_bhrb(u64 pmu_bhrb_filter)
|
|
{
|
|
/* Enable BHRB filter in PMU */
|
|
mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
|
|
}
|
|
|
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
|
|
|
/*
|
|
* Table of generalized cache-related events.
|
|
* 0 means not supported, -1 means nonsensical, other values
|
|
* are event codes.
|
|
*/
|
|
static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
|
[ C(L1D) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
|
|
[ C(RESULT_MISS) ] = PM_LD_MISS_L1,
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
[ C(RESULT_MISS) ] = PM_ST_MISS_L1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_L1_PREF,
|
|
[ C(RESULT_MISS) ] = 0,
|
|
},
|
|
},
|
|
[ C(L1I) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
|
|
[ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
|
|
[ C(RESULT_MISS) ] = 0,
|
|
},
|
|
},
|
|
[ C(LL) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
|
|
[ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_L2_ST,
|
|
[ C(RESULT_MISS) ] = PM_L2_ST_MISS,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
|
|
[ C(RESULT_MISS) ] = 0,
|
|
},
|
|
},
|
|
[ C(DTLB) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
[ C(RESULT_MISS) ] = PM_DTLB_MISS,
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
},
|
|
[ C(ITLB) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
[ C(RESULT_MISS) ] = PM_ITLB_MISS,
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
},
|
|
[ C(BPU) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = PM_BRU_FIN,
|
|
[ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
},
|
|
[ C(NODE) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
},
|
|
};
|
|
|
|
#undef C
|
|
|
|
static struct power_pmu power8_pmu = {
|
|
.name = "POWER8",
|
|
.n_counter = MAX_PMU_COUNTERS,
|
|
.max_alternatives = MAX_ALT + 1,
|
|
.add_fields = ISA207_ADD_FIELDS,
|
|
.test_adder = ISA207_TEST_ADDER,
|
|
.compute_mmcr = power8_compute_mmcr,
|
|
.config_bhrb = power8_config_bhrb,
|
|
.bhrb_filter_map = power8_bhrb_filter_map,
|
|
.get_constraint = power8_get_constraint,
|
|
.get_alternatives = power8_get_alternatives,
|
|
.disable_pmc = power8_disable_pmc,
|
|
.flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
|
|
.n_generic = ARRAY_SIZE(power8_generic_events),
|
|
.generic_events = power8_generic_events,
|
|
.cache_events = &power8_cache_events,
|
|
.attr_groups = power8_pmu_attr_groups,
|
|
.bhrb_nr = 32,
|
|
};
|
|
|
|
static int __init init_power8_pmu(void)
|
|
{
|
|
int rc;
|
|
|
|
if (!cur_cpu_spec->oprofile_cpu_type ||
|
|
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
|
|
return -ENODEV;
|
|
|
|
rc = register_power_pmu(&power8_pmu);
|
|
if (rc)
|
|
return rc;
|
|
|
|
/* Tell userspace that EBB is supported */
|
|
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
|
|
|
|
if (cpu_has_feature(CPU_FTR_PMAO_BUG))
|
|
pr_info("PMAO restore workaround active.\n");
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(init_power8_pmu);
|