mirror of https://gitee.com/openkylin/linux.git
746 lines
17 KiB
C
746 lines
17 KiB
C
/*
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* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/platform_device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <mach/netx-regs.h>
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/* We've been assigned a range on the "Low-density serial ports" major */
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#define SERIAL_NX_MAJOR 204
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#define MINOR_START 170
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enum uart_regs {
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UART_DR = 0x00,
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UART_SR = 0x04,
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UART_LINE_CR = 0x08,
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UART_BAUDDIV_MSB = 0x0c,
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UART_BAUDDIV_LSB = 0x10,
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UART_CR = 0x14,
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UART_FR = 0x18,
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UART_IIR = 0x1c,
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UART_ILPR = 0x20,
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UART_RTS_CR = 0x24,
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UART_RTS_LEAD = 0x28,
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UART_RTS_TRAIL = 0x2c,
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UART_DRV_ENABLE = 0x30,
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UART_BRM_CR = 0x34,
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UART_RXFIFO_IRQLEVEL = 0x38,
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UART_TXFIFO_IRQLEVEL = 0x3c,
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};
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#define SR_FE (1<<0)
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#define SR_PE (1<<1)
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#define SR_BE (1<<2)
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#define SR_OE (1<<3)
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#define LINE_CR_BRK (1<<0)
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#define LINE_CR_PEN (1<<1)
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#define LINE_CR_EPS (1<<2)
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#define LINE_CR_STP2 (1<<3)
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#define LINE_CR_FEN (1<<4)
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#define LINE_CR_5BIT (0<<5)
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#define LINE_CR_6BIT (1<<5)
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#define LINE_CR_7BIT (2<<5)
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#define LINE_CR_8BIT (3<<5)
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#define LINE_CR_BITS_MASK (3<<5)
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#define CR_UART_EN (1<<0)
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#define CR_SIREN (1<<1)
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#define CR_SIRLP (1<<2)
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#define CR_MSIE (1<<3)
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#define CR_RIE (1<<4)
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#define CR_TIE (1<<5)
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#define CR_RTIE (1<<6)
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#define CR_LBE (1<<7)
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#define FR_CTS (1<<0)
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#define FR_DSR (1<<1)
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#define FR_DCD (1<<2)
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#define FR_BUSY (1<<3)
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#define FR_RXFE (1<<4)
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#define FR_TXFF (1<<5)
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#define FR_RXFF (1<<6)
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#define FR_TXFE (1<<7)
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#define IIR_MIS (1<<0)
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#define IIR_RIS (1<<1)
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#define IIR_TIS (1<<2)
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#define IIR_RTIS (1<<3)
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#define IIR_MASK 0xf
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#define RTS_CR_AUTO (1<<0)
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#define RTS_CR_RTS (1<<1)
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#define RTS_CR_COUNT (1<<2)
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#define RTS_CR_MOD2 (1<<3)
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#define RTS_CR_RTS_POL (1<<4)
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#define RTS_CR_CTS_CTR (1<<5)
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#define RTS_CR_CTS_POL (1<<6)
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#define RTS_CR_STICK (1<<7)
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#define UART_PORT_SIZE 0x40
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#define DRIVER_NAME "netx-uart"
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struct netx_port {
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struct uart_port port;
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};
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static void netx_stop_tx(struct uart_port *port)
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{
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unsigned int val;
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val = readl(port->membase + UART_CR);
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writel(val & ~CR_TIE, port->membase + UART_CR);
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}
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static void netx_stop_rx(struct uart_port *port)
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{
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unsigned int val;
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val = readl(port->membase + UART_CR);
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writel(val & ~CR_RIE, port->membase + UART_CR);
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}
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static void netx_enable_ms(struct uart_port *port)
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{
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unsigned int val;
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val = readl(port->membase + UART_CR);
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writel(val | CR_MSIE, port->membase + UART_CR);
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}
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static inline void netx_transmit_buffer(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (port->x_char) {
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writel(port->x_char, port->membase + UART_DR);
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port->icount.tx++;
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port->x_char = 0;
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return;
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}
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if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
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netx_stop_tx(port);
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return;
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}
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do {
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/* send xmit->buf[xmit->tail]
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* out the port here */
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writel(xmit->buf[xmit->tail], port->membase + UART_DR);
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xmit->tail = (xmit->tail + 1) &
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(UART_XMIT_SIZE - 1);
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port->icount.tx++;
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if (uart_circ_empty(xmit))
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break;
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} while (!(readl(port->membase + UART_FR) & FR_TXFF));
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if (uart_circ_empty(xmit))
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netx_stop_tx(port);
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}
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static void netx_start_tx(struct uart_port *port)
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{
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writel(
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readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
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if (!(readl(port->membase + UART_FR) & FR_TXFF))
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netx_transmit_buffer(port);
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}
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static unsigned int netx_tx_empty(struct uart_port *port)
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{
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return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
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}
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static void netx_txint(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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netx_stop_tx(port);
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return;
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}
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netx_transmit_buffer(port);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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static void netx_rxint(struct uart_port *port, unsigned long *flags)
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{
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unsigned char rx, flg, status;
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while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
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rx = readl(port->membase + UART_DR);
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flg = TTY_NORMAL;
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port->icount.rx++;
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status = readl(port->membase + UART_SR);
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if (status & SR_BE) {
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writel(0, port->membase + UART_SR);
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if (uart_handle_break(port))
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continue;
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}
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if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
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if (status & SR_PE)
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port->icount.parity++;
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else if (status & SR_FE)
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port->icount.frame++;
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if (status & SR_OE)
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port->icount.overrun++;
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status &= port->read_status_mask;
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if (status & SR_BE)
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flg = TTY_BREAK;
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else if (status & SR_PE)
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flg = TTY_PARITY;
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else if (status & SR_FE)
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flg = TTY_FRAME;
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}
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if (uart_handle_sysrq_char(port, rx))
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continue;
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uart_insert_char(port, status, SR_OE, rx, flg);
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}
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spin_unlock_irqrestore(&port->lock, *flags);
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tty_flip_buffer_push(&port->state->port);
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spin_lock_irqsave(&port->lock, *flags);
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}
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static irqreturn_t netx_int(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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unsigned long flags;
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unsigned char status;
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spin_lock_irqsave(&port->lock,flags);
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status = readl(port->membase + UART_IIR) & IIR_MASK;
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while (status) {
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if (status & IIR_RIS)
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netx_rxint(port, &flags);
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if (status & IIR_TIS)
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netx_txint(port);
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if (status & IIR_MIS) {
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if (readl(port->membase + UART_FR) & FR_CTS)
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uart_handle_cts_change(port, 1);
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else
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uart_handle_cts_change(port, 0);
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}
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writel(0, port->membase + UART_IIR);
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status = readl(port->membase + UART_IIR) & IIR_MASK;
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}
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spin_unlock_irqrestore(&port->lock,flags);
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return IRQ_HANDLED;
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}
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static unsigned int netx_get_mctrl(struct uart_port *port)
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{
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unsigned int ret = TIOCM_DSR | TIOCM_CAR;
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if (readl(port->membase + UART_FR) & FR_CTS)
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ret |= TIOCM_CTS;
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return ret;
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}
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static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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unsigned int val;
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/* FIXME: Locking needed ? */
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if (mctrl & TIOCM_RTS) {
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val = readl(port->membase + UART_RTS_CR);
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writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
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}
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}
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static void netx_break_ctl(struct uart_port *port, int break_state)
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{
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unsigned int line_cr;
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spin_lock_irq(&port->lock);
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line_cr = readl(port->membase + UART_LINE_CR);
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if (break_state != 0)
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line_cr |= LINE_CR_BRK;
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else
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line_cr &= ~LINE_CR_BRK;
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writel(line_cr, port->membase + UART_LINE_CR);
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spin_unlock_irq(&port->lock);
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}
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static int netx_startup(struct uart_port *port)
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{
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int ret;
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ret = request_irq(port->irq, netx_int, 0,
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DRIVER_NAME, port);
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if (ret) {
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dev_err(port->dev, "unable to grab irq%d\n",port->irq);
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goto exit;
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}
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writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
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port->membase + UART_LINE_CR);
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writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
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port->membase + UART_CR);
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exit:
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return ret;
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}
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static void netx_shutdown(struct uart_port *port)
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{
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writel(0, port->membase + UART_CR) ;
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free_irq(port->irq, port);
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}
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static void
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netx_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud, quot;
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unsigned char old_cr;
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unsigned char line_cr = LINE_CR_FEN;
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unsigned char rts_cr = 0;
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switch (termios->c_cflag & CSIZE) {
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case CS5:
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line_cr |= LINE_CR_5BIT;
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break;
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case CS6:
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line_cr |= LINE_CR_6BIT;
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break;
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case CS7:
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line_cr |= LINE_CR_7BIT;
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break;
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case CS8:
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line_cr |= LINE_CR_8BIT;
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break;
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}
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if (termios->c_cflag & CSTOPB)
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line_cr |= LINE_CR_STP2;
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if (termios->c_cflag & PARENB) {
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line_cr |= LINE_CR_PEN;
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if (!(termios->c_cflag & PARODD))
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line_cr |= LINE_CR_EPS;
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}
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if (termios->c_cflag & CRTSCTS)
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rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
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baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
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quot = baud * 4096;
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quot /= 1000;
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quot *= 256;
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quot /= 100000;
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spin_lock_irq(&port->lock);
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uart_update_timeout(port, termios->c_cflag, baud);
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old_cr = readl(port->membase + UART_CR);
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/* disable interrupts */
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writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
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port->membase + UART_CR);
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/* drain transmitter */
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while (readl(port->membase + UART_FR) & FR_BUSY);
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/* disable UART */
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writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
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/* modem status interrupts */
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old_cr &= ~CR_MSIE;
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if (UART_ENABLE_MS(port, termios->c_cflag))
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old_cr |= CR_MSIE;
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writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
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writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
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writel(line_cr, port->membase + UART_LINE_CR);
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writel(rts_cr, port->membase + UART_RTS_CR);
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/*
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* Characters to ignore
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*/
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port->ignore_status_mask = 0;
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if (termios->c_iflag & IGNPAR)
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port->ignore_status_mask |= SR_PE;
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if (termios->c_iflag & IGNBRK) {
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port->ignore_status_mask |= SR_BE;
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/*
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* If we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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*/
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if (termios->c_iflag & IGNPAR)
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port->ignore_status_mask |= SR_PE;
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}
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port->read_status_mask = 0;
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if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
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port->read_status_mask |= SR_BE;
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if (termios->c_iflag & INPCK)
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port->read_status_mask |= SR_PE | SR_FE;
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writel(old_cr, port->membase + UART_CR);
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spin_unlock_irq(&port->lock);
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}
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static const char *netx_type(struct uart_port *port)
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{
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return port->type == PORT_NETX ? "NETX" : NULL;
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}
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static void netx_release_port(struct uart_port *port)
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{
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release_mem_region(port->mapbase, UART_PORT_SIZE);
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}
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static int netx_request_port(struct uart_port *port)
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{
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return request_mem_region(port->mapbase, UART_PORT_SIZE,
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DRIVER_NAME) != NULL ? 0 : -EBUSY;
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}
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static void netx_config_port(struct uart_port *port, int flags)
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{
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if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
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port->type = PORT_NETX;
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}
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static int
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netx_verify_port(struct uart_port *port, struct serial_struct *ser)
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{
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int ret = 0;
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if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
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ret = -EINVAL;
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return ret;
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}
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static struct uart_ops netx_pops = {
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.tx_empty = netx_tx_empty,
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.set_mctrl = netx_set_mctrl,
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.get_mctrl = netx_get_mctrl,
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.stop_tx = netx_stop_tx,
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.start_tx = netx_start_tx,
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.stop_rx = netx_stop_rx,
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.enable_ms = netx_enable_ms,
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.break_ctl = netx_break_ctl,
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.startup = netx_startup,
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.shutdown = netx_shutdown,
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.set_termios = netx_set_termios,
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.type = netx_type,
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.release_port = netx_release_port,
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.request_port = netx_request_port,
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.config_port = netx_config_port,
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.verify_port = netx_verify_port,
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};
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static struct netx_port netx_ports[] = {
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{
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.port = {
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.type = PORT_NETX,
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.iotype = UPIO_MEM,
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.membase = (char __iomem *)io_p2v(NETX_PA_UART0),
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.mapbase = NETX_PA_UART0,
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.irq = NETX_IRQ_UART0,
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.uartclk = 100000000,
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.fifosize = 16,
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.flags = UPF_BOOT_AUTOCONF,
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.ops = &netx_pops,
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.line = 0,
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},
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}, {
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.port = {
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.type = PORT_NETX,
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.iotype = UPIO_MEM,
|
|
.membase = (char __iomem *)io_p2v(NETX_PA_UART1),
|
|
.mapbase = NETX_PA_UART1,
|
|
.irq = NETX_IRQ_UART1,
|
|
.uartclk = 100000000,
|
|
.fifosize = 16,
|
|
.flags = UPF_BOOT_AUTOCONF,
|
|
.ops = &netx_pops,
|
|
.line = 1,
|
|
},
|
|
}, {
|
|
.port = {
|
|
.type = PORT_NETX,
|
|
.iotype = UPIO_MEM,
|
|
.membase = (char __iomem *)io_p2v(NETX_PA_UART2),
|
|
.mapbase = NETX_PA_UART2,
|
|
.irq = NETX_IRQ_UART2,
|
|
.uartclk = 100000000,
|
|
.fifosize = 16,
|
|
.flags = UPF_BOOT_AUTOCONF,
|
|
.ops = &netx_pops,
|
|
.line = 2,
|
|
},
|
|
}
|
|
};
|
|
|
|
#ifdef CONFIG_SERIAL_NETX_CONSOLE
|
|
|
|
static void netx_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
while (readl(port->membase + UART_FR) & FR_BUSY);
|
|
writel(ch, port->membase + UART_DR);
|
|
}
|
|
|
|
static void
|
|
netx_console_write(struct console *co, const char *s, unsigned int count)
|
|
{
|
|
struct uart_port *port = &netx_ports[co->index].port;
|
|
unsigned char cr_save;
|
|
|
|
cr_save = readl(port->membase + UART_CR);
|
|
writel(cr_save | CR_UART_EN, port->membase + UART_CR);
|
|
|
|
uart_console_write(port, s, count, netx_console_putchar);
|
|
|
|
while (readl(port->membase + UART_FR) & FR_BUSY);
|
|
writel(cr_save, port->membase + UART_CR);
|
|
}
|
|
|
|
static void __init
|
|
netx_console_get_options(struct uart_port *port, int *baud,
|
|
int *parity, int *bits, int *flow)
|
|
{
|
|
unsigned char line_cr;
|
|
|
|
*baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
|
|
readl(port->membase + UART_BAUDDIV_LSB);
|
|
*baud *= 1000;
|
|
*baud /= 4096;
|
|
*baud *= 1000;
|
|
*baud /= 256;
|
|
*baud *= 100;
|
|
|
|
line_cr = readl(port->membase + UART_LINE_CR);
|
|
*parity = 'n';
|
|
if (line_cr & LINE_CR_PEN) {
|
|
if (line_cr & LINE_CR_EPS)
|
|
*parity = 'e';
|
|
else
|
|
*parity = 'o';
|
|
}
|
|
|
|
switch (line_cr & LINE_CR_BITS_MASK) {
|
|
case LINE_CR_8BIT:
|
|
*bits = 8;
|
|
break;
|
|
case LINE_CR_7BIT:
|
|
*bits = 7;
|
|
break;
|
|
case LINE_CR_6BIT:
|
|
*bits = 6;
|
|
break;
|
|
case LINE_CR_5BIT:
|
|
*bits = 5;
|
|
break;
|
|
}
|
|
|
|
if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
|
|
*flow = 'r';
|
|
}
|
|
|
|
static int __init
|
|
netx_console_setup(struct console *co, char *options)
|
|
{
|
|
struct netx_port *sport;
|
|
int baud = 9600;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
/*
|
|
* Check whether an invalid uart number has been specified, and
|
|
* if so, search for the first available port that does have
|
|
* console support.
|
|
*/
|
|
if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
|
|
co->index = 0;
|
|
sport = &netx_ports[co->index];
|
|
|
|
if (options) {
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
} else {
|
|
/* if the UART is enabled, assume it has been correctly setup
|
|
* by the bootloader and get the options
|
|
*/
|
|
if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
|
|
netx_console_get_options(&sport->port, &baud,
|
|
&parity, &bits, &flow);
|
|
}
|
|
|
|
}
|
|
|
|
return uart_set_options(&sport->port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver netx_reg;
|
|
static struct console netx_console = {
|
|
.name = "ttyNX",
|
|
.write = netx_console_write,
|
|
.device = uart_console_device,
|
|
.setup = netx_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &netx_reg,
|
|
};
|
|
|
|
static int __init netx_console_init(void)
|
|
{
|
|
register_console(&netx_console);
|
|
return 0;
|
|
}
|
|
console_initcall(netx_console_init);
|
|
|
|
#define NETX_CONSOLE &netx_console
|
|
#else
|
|
#define NETX_CONSOLE NULL
|
|
#endif
|
|
|
|
static struct uart_driver netx_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = DRIVER_NAME,
|
|
.dev_name = "ttyNX",
|
|
.major = SERIAL_NX_MAJOR,
|
|
.minor = MINOR_START,
|
|
.nr = ARRAY_SIZE(netx_ports),
|
|
.cons = NETX_CONSOLE,
|
|
};
|
|
|
|
static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct netx_port *sport = platform_get_drvdata(pdev);
|
|
|
|
if (sport)
|
|
uart_suspend_port(&netx_reg, &sport->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int serial_netx_resume(struct platform_device *pdev)
|
|
{
|
|
struct netx_port *sport = platform_get_drvdata(pdev);
|
|
|
|
if (sport)
|
|
uart_resume_port(&netx_reg, &sport->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int serial_netx_probe(struct platform_device *pdev)
|
|
{
|
|
struct uart_port *port = &netx_ports[pdev->id].port;
|
|
|
|
dev_info(&pdev->dev, "initialising\n");
|
|
|
|
port->dev = &pdev->dev;
|
|
|
|
writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
|
|
uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
|
|
platform_set_drvdata(pdev, &netx_ports[pdev->id]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int serial_netx_remove(struct platform_device *pdev)
|
|
{
|
|
struct netx_port *sport = platform_get_drvdata(pdev);
|
|
|
|
if (sport)
|
|
uart_remove_one_port(&netx_reg, &sport->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver serial_netx_driver = {
|
|
.probe = serial_netx_probe,
|
|
.remove = serial_netx_remove,
|
|
|
|
.suspend = serial_netx_suspend,
|
|
.resume = serial_netx_resume,
|
|
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init netx_serial_init(void)
|
|
{
|
|
int ret;
|
|
|
|
printk(KERN_INFO "Serial: NetX driver\n");
|
|
|
|
ret = uart_register_driver(&netx_reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&serial_netx_driver);
|
|
if (ret != 0)
|
|
uart_unregister_driver(&netx_reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit netx_serial_exit(void)
|
|
{
|
|
platform_driver_unregister(&serial_netx_driver);
|
|
uart_unregister_driver(&netx_reg);
|
|
}
|
|
|
|
module_init(netx_serial_init);
|
|
module_exit(netx_serial_exit);
|
|
|
|
MODULE_AUTHOR("Sascha Hauer");
|
|
MODULE_DESCRIPTION("NetX serial port driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|