mirror of https://gitee.com/openkylin/linux.git
1050 lines
26 KiB
C
1050 lines
26 KiB
C
/*
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* Copyright (C) Maxime Coquelin 2015
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* Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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* Gerald Baeza <gerald.baeza@st.com>
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* License terms: GNU General Public License (GPL), version 2
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*
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* Inspired by st-asc.c from STMicroelectronics (c)
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*/
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#if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/dma-direction.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/spinlock.h>
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#include <linux/sysrq.h>
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#include <linux/tty_flip.h>
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#include <linux/tty.h>
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#include "stm32-usart.h"
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static void stm32_stop_tx(struct uart_port *port);
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static void stm32_transmit_chars(struct uart_port *port);
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static inline struct stm32_port *to_stm32_port(struct uart_port *port)
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{
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return container_of(port, struct stm32_port, port);
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}
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static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
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{
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u32 val;
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val = readl_relaxed(port->membase + reg);
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val |= bits;
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writel_relaxed(val, port->membase + reg);
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}
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static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
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{
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u32 val;
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val = readl_relaxed(port->membase + reg);
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val &= ~bits;
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writel_relaxed(val, port->membase + reg);
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}
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static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
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bool threaded)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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enum dma_status status;
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struct dma_tx_state state;
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*sr = readl_relaxed(port->membase + ofs->isr);
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if (threaded && stm32_port->rx_ch) {
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status = dmaengine_tx_status(stm32_port->rx_ch,
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stm32_port->rx_ch->cookie,
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&state);
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if ((status == DMA_IN_PROGRESS) &&
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(*last_res != state.residue))
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return 1;
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else
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return 0;
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} else if (*sr & USART_SR_RXNE) {
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return 1;
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}
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return 0;
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}
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static unsigned long
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stm32_get_char(struct uart_port *port, u32 *sr, int *last_res)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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unsigned long c;
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if (stm32_port->rx_ch) {
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c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
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if ((*last_res) == 0)
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*last_res = RX_BUF_L;
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return c;
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} else {
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return readl_relaxed(port->membase + ofs->rdr);
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}
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}
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static void stm32_receive_chars(struct uart_port *port, bool threaded)
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{
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struct tty_port *tport = &port->state->port;
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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unsigned long c;
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u32 sr;
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char flag;
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static int last_res = RX_BUF_L;
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if (port->irq_wake)
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pm_wakeup_event(tport->tty->dev, 0);
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while (stm32_pending_rx(port, &sr, &last_res, threaded)) {
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sr |= USART_SR_DUMMY_RX;
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c = stm32_get_char(port, &sr, &last_res);
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flag = TTY_NORMAL;
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port->icount.rx++;
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if (sr & USART_SR_ERR_MASK) {
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if (sr & USART_SR_LBD) {
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port->icount.brk++;
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if (uart_handle_break(port))
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continue;
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} else if (sr & USART_SR_ORE) {
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if (ofs->icr != UNDEF_REG)
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writel_relaxed(USART_ICR_ORECF,
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port->membase +
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ofs->icr);
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port->icount.overrun++;
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} else if (sr & USART_SR_PE) {
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port->icount.parity++;
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} else if (sr & USART_SR_FE) {
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port->icount.frame++;
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}
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sr &= port->read_status_mask;
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if (sr & USART_SR_LBD)
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flag = TTY_BREAK;
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else if (sr & USART_SR_PE)
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flag = TTY_PARITY;
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else if (sr & USART_SR_FE)
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flag = TTY_FRAME;
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}
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if (uart_handle_sysrq_char(port, c))
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continue;
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uart_insert_char(port, sr, USART_SR_ORE, c, flag);
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}
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spin_unlock(&port->lock);
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tty_flip_buffer_push(tport);
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spin_lock(&port->lock);
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}
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static void stm32_tx_dma_complete(void *arg)
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{
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struct uart_port *port = arg;
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struct stm32_port *stm32port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
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unsigned int isr;
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int ret;
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ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
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isr,
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(isr & USART_SR_TC),
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10, 100000);
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if (ret)
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dev_err(port->dev, "terminal count not set\n");
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if (ofs->icr == UNDEF_REG)
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stm32_clr_bits(port, ofs->isr, USART_SR_TC);
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else
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stm32_set_bits(port, ofs->icr, USART_CR_TC);
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stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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stm32port->tx_dma_busy = false;
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/* Let's see if we have pending data to send */
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stm32_transmit_chars(port);
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}
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static void stm32_transmit_chars_pio(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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unsigned int isr;
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int ret;
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if (stm32_port->tx_dma_busy) {
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stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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stm32_port->tx_dma_busy = false;
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}
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ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
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isr,
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(isr & USART_SR_TXE),
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10, 100);
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if (ret)
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dev_err(port->dev, "tx empty not set\n");
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stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
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writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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static void stm32_transmit_chars_dma(struct uart_port *port)
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{
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struct stm32_port *stm32port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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struct dma_async_tx_descriptor *desc = NULL;
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dma_cookie_t cookie;
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unsigned int count, i;
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if (stm32port->tx_dma_busy)
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return;
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stm32port->tx_dma_busy = true;
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count = uart_circ_chars_pending(xmit);
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if (count > TX_BUF_L)
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count = TX_BUF_L;
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if (xmit->tail < xmit->head) {
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memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
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} else {
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size_t one = UART_XMIT_SIZE - xmit->tail;
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size_t two;
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if (one > count)
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one = count;
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two = count - one;
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memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
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if (two)
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memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
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}
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desc = dmaengine_prep_slave_single(stm32port->tx_ch,
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stm32port->tx_dma_buf,
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count,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT);
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if (!desc) {
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for (i = count; i > 0; i--)
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stm32_transmit_chars_pio(port);
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return;
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}
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desc->callback = stm32_tx_dma_complete;
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desc->callback_param = port;
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/* Push current DMA TX transaction in the pending queue */
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cookie = dmaengine_submit(desc);
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/* Issue pending DMA TX requests */
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dma_async_issue_pending(stm32port->tx_ch);
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stm32_clr_bits(port, ofs->isr, USART_SR_TC);
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stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
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xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
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port->icount.tx += count;
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}
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static void stm32_transmit_chars(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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if (port->x_char) {
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if (stm32_port->tx_dma_busy)
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stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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writel_relaxed(port->x_char, port->membase + ofs->tdr);
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port->x_char = 0;
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port->icount.tx++;
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if (stm32_port->tx_dma_busy)
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stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
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return;
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}
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if (uart_tx_stopped(port)) {
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stm32_stop_tx(port);
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return;
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}
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if (uart_circ_empty(xmit)) {
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stm32_stop_tx(port);
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return;
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}
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if (stm32_port->tx_ch)
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stm32_transmit_chars_dma(port);
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else
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stm32_transmit_chars_pio(port);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit))
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stm32_stop_tx(port);
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}
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static irqreturn_t stm32_interrupt(int irq, void *ptr)
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{
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struct uart_port *port = ptr;
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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u32 sr;
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spin_lock(&port->lock);
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sr = readl_relaxed(port->membase + ofs->isr);
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if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
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stm32_receive_chars(port, false);
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if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
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stm32_transmit_chars(port);
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spin_unlock(&port->lock);
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if (stm32_port->rx_ch)
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return IRQ_WAKE_THREAD;
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else
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return IRQ_HANDLED;
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}
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static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
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{
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struct uart_port *port = ptr;
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struct stm32_port *stm32_port = to_stm32_port(port);
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spin_lock(&port->lock);
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if (stm32_port->rx_ch)
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stm32_receive_chars(port, true);
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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static unsigned int stm32_tx_empty(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
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}
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static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
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stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
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else
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stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
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}
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static unsigned int stm32_get_mctrl(struct uart_port *port)
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{
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/* This routine is used to get signals of: DCD, DSR, RI, and CTS */
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return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
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}
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/* Transmit stop */
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static void stm32_stop_tx(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
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}
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/* There are probably characters waiting to be transmitted. */
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static void stm32_start_tx(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_circ_empty(xmit))
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return;
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stm32_transmit_chars(port);
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}
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/* Throttle the remote when input buffer is about to overflow. */
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static void stm32_throttle(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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/* Unthrottle the remote, the input buffer can now accept data. */
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static void stm32_unthrottle(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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/* Receive stop */
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static void stm32_stop_rx(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
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}
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/* Handle breaks - ignored by us */
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static void stm32_break_ctl(struct uart_port *port, int break_state)
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{
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}
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static int stm32_startup(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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const char *name = to_platform_device(port->dev)->name;
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u32 val;
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int ret;
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ret = request_threaded_irq(port->irq, stm32_interrupt,
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stm32_threaded_interrupt,
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IRQF_NO_SUSPEND, name, port);
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if (ret)
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return ret;
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val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
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stm32_set_bits(port, ofs->cr1, val);
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return 0;
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}
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static void stm32_shutdown(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct stm32_usart_config *cfg = &stm32_port->info->cfg;
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u32 val;
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val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
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val |= BIT(cfg->uart_enable_bit);
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stm32_clr_bits(port, ofs->cr1, val);
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free_irq(port->irq, port);
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}
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static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
|
|
struct stm32_port *stm32_port = to_stm32_port(port);
|
|
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
|
struct stm32_usart_config *cfg = &stm32_port->info->cfg;
|
|
unsigned int baud;
|
|
u32 usartdiv, mantissa, fraction, oversampling;
|
|
tcflag_t cflag = termios->c_cflag;
|
|
u32 cr1, cr2, cr3;
|
|
unsigned long flags;
|
|
|
|
if (!stm32_port->hw_flow_control)
|
|
cflag &= ~CRTSCTS;
|
|
|
|
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
|
|
|
|
spin_lock_irqsave(&port->lock, flags);
|
|
|
|
/* Stop serial port and reset value */
|
|
writel_relaxed(0, port->membase + ofs->cr1);
|
|
|
|
cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
|
|
cr1 |= BIT(cfg->uart_enable_bit);
|
|
cr2 = 0;
|
|
cr3 = 0;
|
|
|
|
if (cflag & CSTOPB)
|
|
cr2 |= USART_CR2_STOP_2B;
|
|
|
|
if (cflag & PARENB) {
|
|
cr1 |= USART_CR1_PCE;
|
|
if ((cflag & CSIZE) == CS8) {
|
|
if (cfg->has_7bits_data)
|
|
cr1 |= USART_CR1_M0;
|
|
else
|
|
cr1 |= USART_CR1_M;
|
|
}
|
|
}
|
|
|
|
if (cflag & PARODD)
|
|
cr1 |= USART_CR1_PS;
|
|
|
|
port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
|
|
if (cflag & CRTSCTS) {
|
|
port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
|
|
cr3 |= USART_CR3_CTSE;
|
|
}
|
|
|
|
usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
|
|
|
|
/*
|
|
* The USART supports 16 or 8 times oversampling.
|
|
* By default we prefer 16 times oversampling, so that the receiver
|
|
* has a better tolerance to clock deviations.
|
|
* 8 times oversampling is only used to achieve higher speeds.
|
|
*/
|
|
if (usartdiv < 16) {
|
|
oversampling = 8;
|
|
stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
|
|
} else {
|
|
oversampling = 16;
|
|
stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
|
|
}
|
|
|
|
mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
|
|
fraction = usartdiv % oversampling;
|
|
writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
|
|
|
|
uart_update_timeout(port, cflag, baud);
|
|
|
|
port->read_status_mask = USART_SR_ORE;
|
|
if (termios->c_iflag & INPCK)
|
|
port->read_status_mask |= USART_SR_PE | USART_SR_FE;
|
|
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
|
|
port->read_status_mask |= USART_SR_LBD;
|
|
|
|
/* Characters to ignore */
|
|
port->ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
|
|
if (termios->c_iflag & IGNBRK) {
|
|
port->ignore_status_mask |= USART_SR_LBD;
|
|
/*
|
|
* If we're ignoring parity and break indicators,
|
|
* ignore overruns too (for real raw support).
|
|
*/
|
|
if (termios->c_iflag & IGNPAR)
|
|
port->ignore_status_mask |= USART_SR_ORE;
|
|
}
|
|
|
|
/* Ignore all characters if CREAD is not set */
|
|
if ((termios->c_cflag & CREAD) == 0)
|
|
port->ignore_status_mask |= USART_SR_DUMMY_RX;
|
|
|
|
if (stm32_port->rx_ch)
|
|
cr3 |= USART_CR3_DMAR;
|
|
|
|
writel_relaxed(cr3, port->membase + ofs->cr3);
|
|
writel_relaxed(cr2, port->membase + ofs->cr2);
|
|
writel_relaxed(cr1, port->membase + ofs->cr1);
|
|
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
static const char *stm32_type(struct uart_port *port)
|
|
{
|
|
return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
|
|
}
|
|
|
|
static void stm32_release_port(struct uart_port *port)
|
|
{
|
|
}
|
|
|
|
static int stm32_request_port(struct uart_port *port)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void stm32_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE)
|
|
port->type = PORT_STM32;
|
|
}
|
|
|
|
static int
|
|
stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
{
|
|
/* No user changeable parameters */
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void stm32_pm(struct uart_port *port, unsigned int state,
|
|
unsigned int oldstate)
|
|
{
|
|
struct stm32_port *stm32port = container_of(port,
|
|
struct stm32_port, port);
|
|
struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
|
|
struct stm32_usart_config *cfg = &stm32port->info->cfg;
|
|
unsigned long flags = 0;
|
|
|
|
switch (state) {
|
|
case UART_PM_STATE_ON:
|
|
clk_prepare_enable(stm32port->clk);
|
|
break;
|
|
case UART_PM_STATE_OFF:
|
|
spin_lock_irqsave(&port->lock, flags);
|
|
stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
clk_disable_unprepare(stm32port->clk);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const struct uart_ops stm32_uart_ops = {
|
|
.tx_empty = stm32_tx_empty,
|
|
.set_mctrl = stm32_set_mctrl,
|
|
.get_mctrl = stm32_get_mctrl,
|
|
.stop_tx = stm32_stop_tx,
|
|
.start_tx = stm32_start_tx,
|
|
.throttle = stm32_throttle,
|
|
.unthrottle = stm32_unthrottle,
|
|
.stop_rx = stm32_stop_rx,
|
|
.break_ctl = stm32_break_ctl,
|
|
.startup = stm32_startup,
|
|
.shutdown = stm32_shutdown,
|
|
.set_termios = stm32_set_termios,
|
|
.pm = stm32_pm,
|
|
.type = stm32_type,
|
|
.release_port = stm32_release_port,
|
|
.request_port = stm32_request_port,
|
|
.config_port = stm32_config_port,
|
|
.verify_port = stm32_verify_port,
|
|
};
|
|
|
|
static int stm32_init_port(struct stm32_port *stm32port,
|
|
struct platform_device *pdev)
|
|
{
|
|
struct uart_port *port = &stm32port->port;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
port->iotype = UPIO_MEM;
|
|
port->flags = UPF_BOOT_AUTOCONF;
|
|
port->ops = &stm32_uart_ops;
|
|
port->dev = &pdev->dev;
|
|
port->irq = platform_get_irq(pdev, 0);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
port->membase = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(port->membase))
|
|
return PTR_ERR(port->membase);
|
|
port->mapbase = res->start;
|
|
|
|
spin_lock_init(&port->lock);
|
|
|
|
stm32port->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(stm32port->clk))
|
|
return PTR_ERR(stm32port->clk);
|
|
|
|
/* Ensure that clk rate is correct by enabling the clk */
|
|
ret = clk_prepare_enable(stm32port->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
stm32port->port.uartclk = clk_get_rate(stm32port->clk);
|
|
if (!stm32port->port.uartclk)
|
|
ret = -EINVAL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
int id;
|
|
|
|
if (!np)
|
|
return NULL;
|
|
|
|
id = of_alias_get_id(np, "serial");
|
|
if (id < 0)
|
|
id = 0;
|
|
|
|
if (WARN_ON(id >= STM32_MAX_PORTS))
|
|
return NULL;
|
|
|
|
stm32_ports[id].hw_flow_control = of_property_read_bool(np,
|
|
"st,hw-flow-ctrl");
|
|
stm32_ports[id].port.line = id;
|
|
return &stm32_ports[id];
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id stm32_match[] = {
|
|
{ .compatible = "st,stm32-usart", .data = &stm32f4_info},
|
|
{ .compatible = "st,stm32-uart", .data = &stm32f4_info},
|
|
{ .compatible = "st,stm32f7-usart", .data = &stm32f7_info},
|
|
{ .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, stm32_match);
|
|
#endif
|
|
|
|
static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
|
|
struct platform_device *pdev)
|
|
{
|
|
struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
|
|
struct uart_port *port = &stm32port->port;
|
|
struct device *dev = &pdev->dev;
|
|
struct dma_slave_config config;
|
|
struct dma_async_tx_descriptor *desc = NULL;
|
|
dma_cookie_t cookie;
|
|
int ret;
|
|
|
|
/* Request DMA RX channel */
|
|
stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
|
|
if (!stm32port->rx_ch) {
|
|
dev_info(dev, "rx dma alloc failed\n");
|
|
return -ENODEV;
|
|
}
|
|
stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
|
|
&stm32port->rx_dma_buf,
|
|
GFP_KERNEL);
|
|
if (!stm32port->rx_buf) {
|
|
ret = -ENOMEM;
|
|
goto alloc_err;
|
|
}
|
|
|
|
/* Configure DMA channel */
|
|
memset(&config, 0, sizeof(config));
|
|
config.src_addr = port->mapbase + ofs->rdr;
|
|
config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
|
|
ret = dmaengine_slave_config(stm32port->rx_ch, &config);
|
|
if (ret < 0) {
|
|
dev_err(dev, "rx dma channel config failed\n");
|
|
ret = -ENODEV;
|
|
goto config_err;
|
|
}
|
|
|
|
/* Prepare a DMA cyclic transaction */
|
|
desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
|
|
stm32port->rx_dma_buf,
|
|
RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
|
|
DMA_PREP_INTERRUPT);
|
|
if (!desc) {
|
|
dev_err(dev, "rx dma prep cyclic failed\n");
|
|
ret = -ENODEV;
|
|
goto config_err;
|
|
}
|
|
|
|
/* No callback as dma buffer is drained on usart interrupt */
|
|
desc->callback = NULL;
|
|
desc->callback_param = NULL;
|
|
|
|
/* Push current DMA transaction in the pending queue */
|
|
cookie = dmaengine_submit(desc);
|
|
|
|
/* Issue pending DMA requests */
|
|
dma_async_issue_pending(stm32port->rx_ch);
|
|
|
|
return 0;
|
|
|
|
config_err:
|
|
dma_free_coherent(&pdev->dev,
|
|
RX_BUF_L, stm32port->rx_buf,
|
|
stm32port->rx_dma_buf);
|
|
|
|
alloc_err:
|
|
dma_release_channel(stm32port->rx_ch);
|
|
stm32port->rx_ch = NULL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
|
|
struct platform_device *pdev)
|
|
{
|
|
struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
|
|
struct uart_port *port = &stm32port->port;
|
|
struct device *dev = &pdev->dev;
|
|
struct dma_slave_config config;
|
|
int ret;
|
|
|
|
stm32port->tx_dma_busy = false;
|
|
|
|
/* Request DMA TX channel */
|
|
stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
|
|
if (!stm32port->tx_ch) {
|
|
dev_info(dev, "tx dma alloc failed\n");
|
|
return -ENODEV;
|
|
}
|
|
stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
|
|
&stm32port->tx_dma_buf,
|
|
GFP_KERNEL);
|
|
if (!stm32port->tx_buf) {
|
|
ret = -ENOMEM;
|
|
goto alloc_err;
|
|
}
|
|
|
|
/* Configure DMA channel */
|
|
memset(&config, 0, sizeof(config));
|
|
config.dst_addr = port->mapbase + ofs->tdr;
|
|
config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
|
|
ret = dmaengine_slave_config(stm32port->tx_ch, &config);
|
|
if (ret < 0) {
|
|
dev_err(dev, "tx dma channel config failed\n");
|
|
ret = -ENODEV;
|
|
goto config_err;
|
|
}
|
|
|
|
return 0;
|
|
|
|
config_err:
|
|
dma_free_coherent(&pdev->dev,
|
|
TX_BUF_L, stm32port->tx_buf,
|
|
stm32port->tx_dma_buf);
|
|
|
|
alloc_err:
|
|
dma_release_channel(stm32port->tx_ch);
|
|
stm32port->tx_ch = NULL;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_serial_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct stm32_port *stm32port;
|
|
int ret;
|
|
|
|
stm32port = stm32_of_get_stm32_port(pdev);
|
|
if (!stm32port)
|
|
return -ENODEV;
|
|
|
|
match = of_match_device(stm32_match, &pdev->dev);
|
|
if (match && match->data)
|
|
stm32port->info = (struct stm32_usart_info *)match->data;
|
|
else
|
|
return -EINVAL;
|
|
|
|
ret = stm32_init_port(stm32port, pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = stm32_of_dma_rx_probe(stm32port, pdev);
|
|
if (ret)
|
|
dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
|
|
|
|
ret = stm32_of_dma_tx_probe(stm32port, pdev);
|
|
if (ret)
|
|
dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
|
|
|
|
platform_set_drvdata(pdev, &stm32port->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_serial_remove(struct platform_device *pdev)
|
|
{
|
|
struct uart_port *port = platform_get_drvdata(pdev);
|
|
struct stm32_port *stm32_port = to_stm32_port(port);
|
|
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
|
|
|
stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
|
|
|
|
if (stm32_port->rx_ch)
|
|
dma_release_channel(stm32_port->rx_ch);
|
|
|
|
if (stm32_port->rx_dma_buf)
|
|
dma_free_coherent(&pdev->dev,
|
|
RX_BUF_L, stm32_port->rx_buf,
|
|
stm32_port->rx_dma_buf);
|
|
|
|
stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
|
|
|
|
if (stm32_port->tx_ch)
|
|
dma_release_channel(stm32_port->tx_ch);
|
|
|
|
if (stm32_port->tx_dma_buf)
|
|
dma_free_coherent(&pdev->dev,
|
|
TX_BUF_L, stm32_port->tx_buf,
|
|
stm32_port->tx_dma_buf);
|
|
|
|
clk_disable_unprepare(stm32_port->clk);
|
|
|
|
return uart_remove_one_port(&stm32_usart_driver, port);
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_SERIAL_STM32_CONSOLE
|
|
static void stm32_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
struct stm32_port *stm32_port = to_stm32_port(port);
|
|
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
|
|
|
while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
|
|
cpu_relax();
|
|
|
|
writel_relaxed(ch, port->membase + ofs->tdr);
|
|
}
|
|
|
|
static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
|
|
{
|
|
struct uart_port *port = &stm32_ports[co->index].port;
|
|
struct stm32_port *stm32_port = to_stm32_port(port);
|
|
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
|
struct stm32_usart_config *cfg = &stm32_port->info->cfg;
|
|
unsigned long flags;
|
|
u32 old_cr1, new_cr1;
|
|
int locked = 1;
|
|
|
|
local_irq_save(flags);
|
|
if (port->sysrq)
|
|
locked = 0;
|
|
else if (oops_in_progress)
|
|
locked = spin_trylock(&port->lock);
|
|
else
|
|
spin_lock(&port->lock);
|
|
|
|
/* Save and disable interrupts, enable the transmitter */
|
|
old_cr1 = readl_relaxed(port->membase + ofs->cr1);
|
|
new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
|
|
new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
|
|
writel_relaxed(new_cr1, port->membase + ofs->cr1);
|
|
|
|
uart_console_write(port, s, cnt, stm32_console_putchar);
|
|
|
|
/* Restore interrupt state */
|
|
writel_relaxed(old_cr1, port->membase + ofs->cr1);
|
|
|
|
if (locked)
|
|
spin_unlock(&port->lock);
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static int stm32_console_setup(struct console *co, char *options)
|
|
{
|
|
struct stm32_port *stm32port;
|
|
int baud = 9600;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if (co->index >= STM32_MAX_PORTS)
|
|
return -ENODEV;
|
|
|
|
stm32port = &stm32_ports[co->index];
|
|
|
|
/*
|
|
* This driver does not support early console initialization
|
|
* (use ARM early printk support instead), so we only expect
|
|
* this to be called during the uart port registration when the
|
|
* driver gets probed and the port should be mapped at that point.
|
|
*/
|
|
if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
|
|
return -ENXIO;
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct console stm32_console = {
|
|
.name = STM32_SERIAL_NAME,
|
|
.device = uart_console_device,
|
|
.write = stm32_console_write,
|
|
.setup = stm32_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &stm32_usart_driver,
|
|
};
|
|
|
|
#define STM32_SERIAL_CONSOLE (&stm32_console)
|
|
|
|
#else
|
|
#define STM32_SERIAL_CONSOLE NULL
|
|
#endif /* CONFIG_SERIAL_STM32_CONSOLE */
|
|
|
|
static struct uart_driver stm32_usart_driver = {
|
|
.driver_name = DRIVER_NAME,
|
|
.dev_name = STM32_SERIAL_NAME,
|
|
.major = 0,
|
|
.minor = 0,
|
|
.nr = STM32_MAX_PORTS,
|
|
.cons = STM32_SERIAL_CONSOLE,
|
|
};
|
|
|
|
static struct platform_driver stm32_serial_driver = {
|
|
.probe = stm32_serial_probe,
|
|
.remove = stm32_serial_remove,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = of_match_ptr(stm32_match),
|
|
},
|
|
};
|
|
|
|
static int __init usart_init(void)
|
|
{
|
|
static char banner[] __initdata = "STM32 USART driver initialized";
|
|
int ret;
|
|
|
|
pr_info("%s\n", banner);
|
|
|
|
ret = uart_register_driver(&stm32_usart_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&stm32_serial_driver);
|
|
if (ret)
|
|
uart_unregister_driver(&stm32_usart_driver);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit usart_exit(void)
|
|
{
|
|
platform_driver_unregister(&stm32_serial_driver);
|
|
uart_unregister_driver(&stm32_usart_driver);
|
|
}
|
|
|
|
module_init(usart_init);
|
|
module_exit(usart_exit);
|
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
|
|
MODULE_LICENSE("GPL v2");
|