linux/arch/arm/mach-prima2
Russell King f81309067f ARM: move heavy barrier support out of line
The existing memory barrier macro causes a significant amount of code
to be inserted inline at every call site.  For example, in
gpio_set_irq_type(), we have this for mb():

c0344c08:       f57ff04e        dsb     st
c0344c0c:       e59f8190        ldr     r8, [pc, #400]  ; c0344da4 <gpio_set_irq_type+0x230>
c0344c10:       e3590004        cmp     r9, #4
c0344c14:       e5983014        ldr     r3, [r8, #20]
c0344c18:       0a000054        beq     c0344d70 <gpio_set_irq_type+0x1fc>
c0344c1c:       e3530000        cmp     r3, #0
c0344c20:       0a000004        beq     c0344c38 <gpio_set_irq_type+0xc4>
c0344c24:       e50b2030        str     r2, [fp, #-48]  ; 0xffffffd0
c0344c28:       e50bc034        str     ip, [fp, #-52]  ; 0xffffffcc
c0344c2c:       e12fff33        blx     r3
c0344c30:       e51bc034        ldr     ip, [fp, #-52]  ; 0xffffffcc
c0344c34:       e51b2030        ldr     r2, [fp, #-48]  ; 0xffffffd0
c0344c38:       e5963004        ldr     r3, [r6, #4]

Moving the outer_cache_sync() call out of line reduces the impact of
the barrier:

c0344968:       f57ff04e        dsb     st
c034496c:       e35a0004        cmp     sl, #4
c0344970:       e50b2030        str     r2, [fp, #-48]  ; 0xffffffd0
c0344974:       0a000044        beq     c0344a8c <gpio_set_irq_type+0x1b8>
c0344978:       ebf363dd        bl      c001d8f4 <arm_heavy_mb>
c034497c:       e5953004        ldr     r3, [r5, #4]

This should reduce the cache footprint of this code.  Overall, this
results in a reduction of around 20K in the kernel size:

    text    data      bss      dec     hex filename
10773970  667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old
10754219  667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new

Another advantage to this approach is that we can finally resolve the
issue of SoCs which have their own memory barrier requirements within
multiplatform kernels (such as OMAP.)  Here, the bus interconnects
need additional handling to ensure that writes become visible in the
correct order (eg, between dma_map() operations, writes to DMA
coherent memory, and MMIO accesses.)

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-07-25 15:28:05 +01:00
..
Kconfig ARM: prima2: do not select SMP_ON_UP 2015-02-18 12:20:27 +01:00
Makefile ARM: sirf: move to debug_ll_io_init and drop map_io 2015-01-20 19:56:53 +08:00
Makefile.boot ARM: dtb: move all dtb targets to common Makefile 2012-09-20 22:58:17 -07:00
common.c ARM: make arrays containing machine compatible strings const 2015-02-19 09:44:17 +01:00
common.h ARM: sirf: drop redundant function and marco declaration 2015-02-06 00:31:58 -08:00
headsmp.S ARM: v7 setup function should invalidate L1 cache 2015-06-01 11:30:26 +01:00
hotplug.c ARM: cpu hotplug: remove majority of cache flushing from platforms 2013-04-18 20:08:04 +01:00
platsmp.c ARM: make of_device_ids const 2015-02-19 09:44:25 +01:00
pm.c ARM: move heavy barrier support out of line 2015-07-25 15:28:05 +01:00
pm.h ARM: CSR: PM: add sleep entry for SiRFprimaII 2011-09-21 23:25:59 +08:00
rstc.c ARM: sirf: drop Marco support in reset controller module 2015-01-20 19:56:40 +08:00
rtciobrg.c ARM: sirf: drop Marco machine 2015-01-20 19:56:43 +08:00
sleep.S ARM: CSR: PM: add sleep entry for SiRFprimaII 2011-09-21 23:25:59 +08:00