mirror of https://gitee.com/openkylin/linux.git
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/* linux/arch/arm/plat-s3c24xx/clock.c
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX Core clock control support
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*
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* Based on, and code from linux/arch/arm/mach-versatile/clock.c
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**
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** Copyright (C) 2004 ARM Limited.
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** Written by Deep Blue Solutions Limited.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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/* initialise all the clocks */
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void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
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unsigned long hclk,
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unsigned long pclk)
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{
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clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
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clk_xtal.rate);
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clk_mpll.rate = fclk;
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clk_h.rate = hclk;
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clk_p.rate = pclk;
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clk_f.rate = fclk;
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}
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