mirror of https://gitee.com/openkylin/linux.git
360 lines
9.1 KiB
C
360 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for FPGA Management Engine Error Management
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*
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* Copyright 2019 Intel Corporation, Inc.
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*
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* Authors:
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* Kang Luwei <luwei.kang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Wu Hao <hao.wu@intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Mitchel, Henry <henry.mitchel@intel.com>
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*/
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#include <linux/uaccess.h>
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#include "dfl.h"
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#include "dfl-fme.h"
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#define FME_ERROR_MASK 0x8
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#define FME_ERROR 0x10
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#define MBP_ERROR BIT_ULL(6)
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#define PCIE0_ERROR_MASK 0x18
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#define PCIE0_ERROR 0x20
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#define PCIE1_ERROR_MASK 0x28
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#define PCIE1_ERROR 0x30
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#define FME_FIRST_ERROR 0x38
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#define FME_NEXT_ERROR 0x40
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#define RAS_NONFAT_ERROR_MASK 0x48
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#define RAS_NONFAT_ERROR 0x50
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#define RAS_CATFAT_ERROR_MASK 0x58
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#define RAS_CATFAT_ERROR 0x60
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#define RAS_ERROR_INJECT 0x68
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#define INJECT_ERROR_MASK GENMASK_ULL(2, 0)
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#define ERROR_MASK GENMASK_ULL(63, 0)
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static ssize_t pcie0_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + PCIE0_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static ssize_t pcie0_errors_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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int ret = 0;
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u64 v, val;
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if (kstrtou64(buf, 0, &val))
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK);
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v = readq(base + PCIE0_ERROR);
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if (val == v)
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writeq(v, base + PCIE0_ERROR);
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else
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ret = -EINVAL;
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writeq(0ULL, base + PCIE0_ERROR_MASK);
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mutex_unlock(&pdata->lock);
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return ret ? ret : count;
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}
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static DEVICE_ATTR_RW(pcie0_errors);
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static ssize_t pcie1_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + PCIE1_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static ssize_t pcie1_errors_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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int ret = 0;
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u64 v, val;
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if (kstrtou64(buf, 0, &val))
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK);
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v = readq(base + PCIE1_ERROR);
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if (val == v)
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writeq(v, base + PCIE1_ERROR);
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else
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ret = -EINVAL;
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writeq(0ULL, base + PCIE1_ERROR_MASK);
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mutex_unlock(&pdata->lock);
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return ret ? ret : count;
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}
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static DEVICE_ATTR_RW(pcie1_errors);
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static ssize_t nonfatal_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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return sprintf(buf, "0x%llx\n",
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(unsigned long long)readq(base + RAS_NONFAT_ERROR));
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}
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static DEVICE_ATTR_RO(nonfatal_errors);
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static ssize_t catfatal_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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return sprintf(buf, "0x%llx\n",
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(unsigned long long)readq(base + RAS_CATFAT_ERROR));
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}
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static DEVICE_ATTR_RO(catfatal_errors);
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static ssize_t inject_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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v = readq(base + RAS_ERROR_INJECT);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n",
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(unsigned long long)FIELD_GET(INJECT_ERROR_MASK, v));
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}
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static ssize_t inject_errors_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u8 inject_error;
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u64 v;
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if (kstrtou8(buf, 0, &inject_error))
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return -EINVAL;
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if (inject_error & ~INJECT_ERROR_MASK)
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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v = readq(base + RAS_ERROR_INJECT);
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v &= ~INJECT_ERROR_MASK;
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v |= FIELD_PREP(INJECT_ERROR_MASK, inject_error);
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writeq(v, base + RAS_ERROR_INJECT);
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mutex_unlock(&pdata->lock);
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return count;
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}
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static DEVICE_ATTR_RW(inject_errors);
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static ssize_t fme_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + FME_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static ssize_t fme_errors_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 v, val;
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int ret = 0;
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if (kstrtou64(buf, 0, &val))
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK);
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v = readq(base + FME_ERROR);
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if (val == v)
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writeq(v, base + FME_ERROR);
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else
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ret = -EINVAL;
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/* Workaround: disable MBP_ERROR if feature revision is 0 */
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writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR,
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base + FME_ERROR_MASK);
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mutex_unlock(&pdata->lock);
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return ret ? ret : count;
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}
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static DEVICE_ATTR_RW(fme_errors);
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static ssize_t first_error_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + FME_FIRST_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static DEVICE_ATTR_RO(first_error);
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static ssize_t next_error_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + FME_NEXT_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static DEVICE_ATTR_RO(next_error);
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static struct attribute *fme_global_err_attrs[] = {
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&dev_attr_pcie0_errors.attr,
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&dev_attr_pcie1_errors.attr,
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&dev_attr_nonfatal_errors.attr,
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&dev_attr_catfatal_errors.attr,
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&dev_attr_inject_errors.attr,
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&dev_attr_fme_errors.attr,
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&dev_attr_first_error.attr,
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&dev_attr_next_error.attr,
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NULL,
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};
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static umode_t fme_global_err_attrs_visible(struct kobject *kobj,
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struct attribute *attr, int n)
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{
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struct device *dev = kobj_to_dev(kobj);
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/*
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* sysfs entries are visible only if related private feature is
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* enumerated.
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*/
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if (!dfl_get_feature_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR))
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return 0;
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return attr->mode;
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}
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const struct attribute_group fme_global_err_group = {
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.name = "errors",
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.attrs = fme_global_err_attrs,
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.is_visible = fme_global_err_attrs_visible,
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};
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static void fme_err_mask(struct device *dev, bool mask)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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/* Workaround: keep MBP_ERROR always masked if revision is 0 */
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if (dfl_feature_revision(base))
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writeq(mask ? ERROR_MASK : 0, base + FME_ERROR_MASK);
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else
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writeq(mask ? ERROR_MASK : MBP_ERROR, base + FME_ERROR_MASK);
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writeq(mask ? ERROR_MASK : 0, base + PCIE0_ERROR_MASK);
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writeq(mask ? ERROR_MASK : 0, base + PCIE1_ERROR_MASK);
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writeq(mask ? ERROR_MASK : 0, base + RAS_NONFAT_ERROR_MASK);
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writeq(mask ? ERROR_MASK : 0, base + RAS_CATFAT_ERROR_MASK);
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mutex_unlock(&pdata->lock);
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}
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static int fme_global_err_init(struct platform_device *pdev,
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struct dfl_feature *feature)
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{
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fme_err_mask(&pdev->dev, false);
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return 0;
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}
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static void fme_global_err_uinit(struct platform_device *pdev,
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struct dfl_feature *feature)
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{
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fme_err_mask(&pdev->dev, true);
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}
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const struct dfl_feature_id fme_global_err_id_table[] = {
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{.id = FME_FEATURE_ID_GLOBAL_ERR,},
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{0,}
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};
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const struct dfl_feature_ops fme_global_err_ops = {
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.init = fme_global_err_init,
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.uinit = fme_global_err_uinit,
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};
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