mirror of https://gitee.com/openkylin/linux.git
357 lines
12 KiB
C
357 lines
12 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
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#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
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#define GPLL0_EARLY 0
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#define GPLL0 1
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#define GPLL1_EARLY 2
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#define GPLL1 3
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#define GPLL2_EARLY 4
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#define GPLL2 5
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#define GPLL3_EARLY 6
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#define GPLL3 7
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#define GPLL4_EARLY 8
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#define GPLL4 9
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#define SYSTEM_NOC_CLK_SRC 10
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#define CONFIG_NOC_CLK_SRC 11
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#define PERIPH_NOC_CLK_SRC 12
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#define MMSS_BIMC_GFX_CLK_SRC 13
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#define USB30_MASTER_CLK_SRC 14
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#define USB30_MOCK_UTMI_CLK_SRC 15
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#define USB3_PHY_AUX_CLK_SRC 16
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#define USB20_MASTER_CLK_SRC 17
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#define USB20_MOCK_UTMI_CLK_SRC 18
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#define SDCC1_APPS_CLK_SRC 19
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#define SDCC1_ICE_CORE_CLK_SRC 20
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#define SDCC2_APPS_CLK_SRC 21
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#define SDCC3_APPS_CLK_SRC 22
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#define SDCC4_APPS_CLK_SRC 23
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25
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#define BLSP1_UART1_APPS_CLK_SRC 26
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28
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#define BLSP1_UART2_APPS_CLK_SRC 29
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
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#define BLSP1_UART3_APPS_CLK_SRC 32
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34
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#define BLSP1_UART4_APPS_CLK_SRC 35
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37
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#define BLSP1_UART5_APPS_CLK_SRC 38
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40
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#define BLSP1_UART6_APPS_CLK_SRC 41
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43
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#define BLSP2_UART1_APPS_CLK_SRC 44
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46
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#define BLSP2_UART2_APPS_CLK_SRC 47
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
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#define BLSP2_UART3_APPS_CLK_SRC 50
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52
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#define BLSP2_UART4_APPS_CLK_SRC 53
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#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
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#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55
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#define BLSP2_UART5_APPS_CLK_SRC 56
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#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57
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#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58
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#define BLSP2_UART6_APPS_CLK_SRC 59
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#define PDM2_CLK_SRC 60
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#define TSIF_REF_CLK_SRC 61
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#define CE1_CLK_SRC 62
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#define GCC_SLEEP_CLK_SRC 63
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#define BIMC_CLK_SRC 64
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#define HMSS_AHB_CLK_SRC 65
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#define BIMC_HMSS_AXI_CLK_SRC 66
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#define HMSS_RBCPR_CLK_SRC 67
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#define HMSS_GPLL0_CLK_SRC 68
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#define GP1_CLK_SRC 69
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#define GP2_CLK_SRC 70
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#define GP3_CLK_SRC 71
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#define PCIE_AUX_CLK_SRC 72
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#define UFS_AXI_CLK_SRC 73
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#define UFS_ICE_CORE_CLK_SRC 74
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#define QSPI_SER_CLK_SRC 75
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#define GCC_SYS_NOC_AXI_CLK 76
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#define GCC_SYS_NOC_HMSS_AHB_CLK 77
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#define GCC_SNOC_CNOC_AHB_CLK 78
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#define GCC_SNOC_PNOC_AHB_CLK 79
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#define GCC_SYS_NOC_AT_CLK 80
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#define GCC_SYS_NOC_USB3_AXI_CLK 81
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#define GCC_SYS_NOC_UFS_AXI_CLK 82
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#define GCC_CFG_NOC_AHB_CLK 83
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#define GCC_PERIPH_NOC_AHB_CLK 84
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#define GCC_PERIPH_NOC_USB20_AHB_CLK 85
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#define GCC_TIC_CLK 86
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#define GCC_IMEM_AXI_CLK 87
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#define GCC_MMSS_SYS_NOC_AXI_CLK 88
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#define GCC_MMSS_NOC_CFG_AHB_CLK 89
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#define GCC_MMSS_BIMC_GFX_CLK 90
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#define GCC_USB30_MASTER_CLK 91
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#define GCC_USB30_SLEEP_CLK 92
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#define GCC_USB30_MOCK_UTMI_CLK 93
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#define GCC_USB3_PHY_AUX_CLK 94
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#define GCC_USB3_PHY_PIPE_CLK 95
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#define GCC_USB20_MASTER_CLK 96
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#define GCC_USB20_SLEEP_CLK 97
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#define GCC_USB20_MOCK_UTMI_CLK 98
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
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#define GCC_SDCC1_APPS_CLK 100
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#define GCC_SDCC1_AHB_CLK 101
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#define GCC_SDCC1_ICE_CORE_CLK 102
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#define GCC_SDCC2_APPS_CLK 103
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#define GCC_SDCC2_AHB_CLK 104
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#define GCC_SDCC3_APPS_CLK 105
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#define GCC_SDCC3_AHB_CLK 106
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#define GCC_SDCC4_APPS_CLK 107
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#define GCC_SDCC4_AHB_CLK 108
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#define GCC_BLSP1_AHB_CLK 109
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#define GCC_BLSP1_SLEEP_CLK 110
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112
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#define GCC_BLSP1_UART1_APPS_CLK 113
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115
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#define GCC_BLSP1_UART2_APPS_CLK 116
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118
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#define GCC_BLSP1_UART3_APPS_CLK 119
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121
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#define GCC_BLSP1_UART4_APPS_CLK 122
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124
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#define GCC_BLSP1_UART5_APPS_CLK 125
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127
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#define GCC_BLSP1_UART6_APPS_CLK 128
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#define GCC_BLSP2_AHB_CLK 129
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#define GCC_BLSP2_SLEEP_CLK 130
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132
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#define GCC_BLSP2_UART1_APPS_CLK 133
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135
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#define GCC_BLSP2_UART2_APPS_CLK 136
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138
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#define GCC_BLSP2_UART3_APPS_CLK 139
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141
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#define GCC_BLSP2_UART4_APPS_CLK 142
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#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143
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#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144
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#define GCC_BLSP2_UART5_APPS_CLK 145
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#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146
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#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147
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#define GCC_BLSP2_UART6_APPS_CLK 148
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#define GCC_PDM_AHB_CLK 149
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#define GCC_PDM_XO4_CLK 150
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#define GCC_PDM2_CLK 151
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#define GCC_PRNG_AHB_CLK 152
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#define GCC_TSIF_AHB_CLK 153
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#define GCC_TSIF_REF_CLK 154
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#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155
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#define GCC_TCSR_AHB_CLK 156
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#define GCC_BOOT_ROM_AHB_CLK 157
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#define GCC_MSG_RAM_AHB_CLK 158
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#define GCC_TLMM_AHB_CLK 159
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#define GCC_TLMM_CLK 160
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#define GCC_MPM_AHB_CLK 161
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#define GCC_SPMI_SER_CLK 162
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#define GCC_SPMI_CNOC_AHB_CLK 163
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#define GCC_CE1_CLK 164
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#define GCC_CE1_AXI_CLK 165
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#define GCC_CE1_AHB_CLK 166
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#define GCC_BIMC_HMSS_AXI_CLK 167
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#define GCC_BIMC_GFX_CLK 168
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#define GCC_HMSS_AHB_CLK 169
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#define GCC_HMSS_SLV_AXI_CLK 170
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#define GCC_HMSS_MSTR_AXI_CLK 171
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#define GCC_HMSS_RBCPR_CLK 172
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#define GCC_GP1_CLK 173
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#define GCC_GP2_CLK 174
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#define GCC_GP3_CLK 175
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#define GCC_PCIE_0_SLV_AXI_CLK 176
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#define GCC_PCIE_0_MSTR_AXI_CLK 177
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#define GCC_PCIE_0_CFG_AHB_CLK 178
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#define GCC_PCIE_0_AUX_CLK 179
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#define GCC_PCIE_0_PIPE_CLK 180
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#define GCC_PCIE_1_SLV_AXI_CLK 181
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#define GCC_PCIE_1_MSTR_AXI_CLK 182
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#define GCC_PCIE_1_CFG_AHB_CLK 183
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#define GCC_PCIE_1_AUX_CLK 184
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#define GCC_PCIE_1_PIPE_CLK 185
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#define GCC_PCIE_2_SLV_AXI_CLK 186
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#define GCC_PCIE_2_MSTR_AXI_CLK 187
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#define GCC_PCIE_2_CFG_AHB_CLK 188
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#define GCC_PCIE_2_AUX_CLK 189
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#define GCC_PCIE_2_PIPE_CLK 190
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#define GCC_PCIE_PHY_CFG_AHB_CLK 191
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#define GCC_PCIE_PHY_AUX_CLK 192
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#define GCC_UFS_AXI_CLK 193
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#define GCC_UFS_AHB_CLK 194
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#define GCC_UFS_TX_CFG_CLK 195
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#define GCC_UFS_RX_CFG_CLK 196
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#define GCC_UFS_TX_SYMBOL_0_CLK 197
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#define GCC_UFS_RX_SYMBOL_0_CLK 198
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#define GCC_UFS_RX_SYMBOL_1_CLK 199
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#define GCC_UFS_UNIPRO_CORE_CLK 200
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#define GCC_UFS_ICE_CORE_CLK 201
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#define GCC_UFS_SYS_CLK_CORE_CLK 202
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#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203
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#define GCC_AGGRE0_SNOC_AXI_CLK 204
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#define GCC_AGGRE0_CNOC_AHB_CLK 205
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#define GCC_SMMU_AGGRE0_AXI_CLK 206
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#define GCC_SMMU_AGGRE0_AHB_CLK 207
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#define GCC_AGGRE1_PNOC_AHB_CLK 208
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#define GCC_AGGRE2_UFS_AXI_CLK 209
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#define GCC_AGGRE2_USB3_AXI_CLK 210
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#define GCC_QSPI_AHB_CLK 211
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#define GCC_QSPI_SER_CLK 212
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#define GCC_USB3_CLKREF_CLK 213
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#define GCC_HDMI_CLKREF_CLK 214
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#define GCC_UFS_CLKREF_CLK 215
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#define GCC_PCIE_CLKREF_CLK 216
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#define GCC_RX2_USB2_CLKREF_CLK 217
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#define GCC_RX1_USB2_CLKREF_CLK 218
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#define GCC_SYSTEM_NOC_BCR 0
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#define GCC_CONFIG_NOC_BCR 1
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#define GCC_PERIPH_NOC_BCR 2
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#define GCC_IMEM_BCR 3
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#define GCC_MMSS_BCR 4
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#define GCC_PIMEM_BCR 5
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#define GCC_QDSS_BCR 6
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#define GCC_USB_30_BCR 7
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#define GCC_USB_20_BCR 8
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#define GCC_QUSB2PHY_PRIM_BCR 9
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#define GCC_QUSB2PHY_SEC_BCR 10
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11
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#define GCC_SDCC1_BCR 12
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#define GCC_SDCC2_BCR 13
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#define GCC_SDCC3_BCR 14
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#define GCC_SDCC4_BCR 15
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#define GCC_BLSP1_BCR 16
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#define GCC_BLSP1_QUP1_BCR 17
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#define GCC_BLSP1_UART1_BCR 18
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#define GCC_BLSP1_QUP2_BCR 19
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#define GCC_BLSP1_UART2_BCR 20
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#define GCC_BLSP1_QUP3_BCR 21
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#define GCC_BLSP1_UART3_BCR 22
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#define GCC_BLSP1_QUP4_BCR 23
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#define GCC_BLSP1_UART4_BCR 24
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#define GCC_BLSP1_QUP5_BCR 25
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#define GCC_BLSP1_UART5_BCR 26
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#define GCC_BLSP1_QUP6_BCR 27
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#define GCC_BLSP1_UART6_BCR 28
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#define GCC_BLSP2_BCR 29
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#define GCC_BLSP2_QUP1_BCR 30
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#define GCC_BLSP2_UART1_BCR 31
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#define GCC_BLSP2_QUP2_BCR 32
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#define GCC_BLSP2_UART2_BCR 33
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#define GCC_BLSP2_QUP3_BCR 34
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#define GCC_BLSP2_UART3_BCR 35
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#define GCC_BLSP2_QUP4_BCR 36
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#define GCC_BLSP2_UART4_BCR 37
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#define GCC_BLSP2_QUP5_BCR 38
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#define GCC_BLSP2_UART5_BCR 39
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#define GCC_BLSP2_QUP6_BCR 40
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#define GCC_BLSP2_UART6_BCR 41
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#define GCC_PDM_BCR 42
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#define GCC_PRNG_BCR 43
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#define GCC_TSIF_BCR 44
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#define GCC_TCSR_BCR 45
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#define GCC_BOOT_ROM_BCR 46
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#define GCC_MSG_RAM_BCR 47
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#define GCC_TLMM_BCR 48
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#define GCC_MPM_BCR 49
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#define GCC_SEC_CTRL_BCR 50
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#define GCC_SPMI_BCR 51
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#define GCC_SPDM_BCR 52
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#define GCC_CE1_BCR 53
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#define GCC_BIMC_BCR 54
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#define GCC_SNOC_BUS_TIMEOUT0_BCR 55
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#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
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#define GCC_SNOC_BUS_TIMEOUT1_BCR 57
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#define GCC_SNOC_BUS_TIMEOUT3_BCR 58
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#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59
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#define GCC_PNOC_BUS_TIMEOUT0_BCR 60
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#define GCC_PNOC_BUS_TIMEOUT1_BCR 61
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#define GCC_PNOC_BUS_TIMEOUT2_BCR 62
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#define GCC_PNOC_BUS_TIMEOUT3_BCR 63
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#define GCC_PNOC_BUS_TIMEOUT4_BCR 64
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#define GCC_CNOC_BUS_TIMEOUT0_BCR 65
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#define GCC_CNOC_BUS_TIMEOUT1_BCR 66
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#define GCC_CNOC_BUS_TIMEOUT2_BCR 67
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#define GCC_CNOC_BUS_TIMEOUT3_BCR 68
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#define GCC_CNOC_BUS_TIMEOUT4_BCR 69
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#define GCC_CNOC_BUS_TIMEOUT5_BCR 70
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#define GCC_CNOC_BUS_TIMEOUT6_BCR 71
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#define GCC_CNOC_BUS_TIMEOUT7_BCR 72
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#define GCC_CNOC_BUS_TIMEOUT8_BCR 73
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#define GCC_CNOC_BUS_TIMEOUT9_BCR 74
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#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75
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#define GCC_APB2JTAG_BCR 76
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#define GCC_RBCPR_CX_BCR 77
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#define GCC_RBCPR_MX_BCR 78
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#define GCC_PCIE_0_BCR 79
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#define GCC_PCIE_0_PHY_BCR 80
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#define GCC_PCIE_1_BCR 81
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#define GCC_PCIE_1_PHY_BCR 82
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#define GCC_PCIE_2_BCR 83
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#define GCC_PCIE_2_PHY_BCR 84
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#define GCC_PCIE_PHY_BCR 85
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#define GCC_DCD_BCR 86
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#define GCC_OBT_ODT_BCR 87
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#define GCC_UFS_BCR 88
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#define GCC_SSC_BCR 89
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#define GCC_VS_BCR 90
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#define GCC_AGGRE0_NOC_BCR 91
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#define GCC_AGGRE1_NOC_BCR 92
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#define GCC_AGGRE2_NOC_BCR 93
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#define GCC_DCC_BCR 94
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#define GCC_IPA_BCR 95
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#define GCC_QSPI_BCR 96
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#define GCC_SKL_BCR 97
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#define GCC_MSMPU_BCR 98
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#define GCC_MSS_Q6_BCR 99
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#define GCC_QREFS_VBG_CAL_BCR 100
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#define GCC_PCIE_PHY_COM_BCR 101
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#define GCC_PCIE_PHY_COM_NOCSR_BCR 102
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#define GCC_USB3_PHY_BCR 103
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#define GCC_USB3PHY_PHY_BCR 104
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#define GCC_MSS_RESTART 105
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/* Indexes for GDSCs */
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#define AGGRE0_NOC_GDSC 0
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#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1
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#define HLOS1_VOTE_LPASS_ADSP_GDSC 2
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#define HLOS1_VOTE_LPASS_CORE_GDSC 3
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#define USB30_GDSC 4
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#define PCIE0_GDSC 5
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#define PCIE1_GDSC 6
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#define PCIE2_GDSC 7
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#define UFS_GDSC 8
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#endif
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