mirror of https://gitee.com/openkylin/linux.git
451 lines
9.3 KiB
C
451 lines
9.3 KiB
C
/* Geode LX framebuffer driver
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*
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* Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
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* Copyright (c) 2008 Andres Salomon <dilinger@debian.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _LXFB_H_
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#define _LXFB_H_
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#include <linux/fb.h>
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#define GP_REG_COUNT (0x7c / 4)
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#define DC_REG_COUNT (0xf0 / 4)
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#define VP_REG_COUNT (0x158 / 8)
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#define FP_REG_COUNT (0x60 / 8)
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#define DC_PAL_COUNT 0x104
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#define DC_HFILT_COUNT 0x100
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#define DC_VFILT_COUNT 0x100
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#define VP_COEFF_SIZE 0x1000
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#define OUTPUT_CRT 0x01
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#define OUTPUT_PANEL 0x02
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struct lxfb_par {
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int output;
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void __iomem *gp_regs;
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void __iomem *dc_regs;
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void __iomem *vp_regs;
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#ifdef CONFIG_PM
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int powered_down;
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/* register state, for power mgmt functionality */
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struct {
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uint64_t padsel;
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uint64_t dotpll;
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uint64_t dfglcfg;
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uint64_t dcspare;
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} msr;
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uint32_t gp[GP_REG_COUNT];
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uint32_t dc[DC_REG_COUNT];
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uint64_t vp[VP_REG_COUNT];
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uint64_t fp[FP_REG_COUNT];
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uint32_t pal[DC_PAL_COUNT];
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uint32_t hcoeff[DC_HFILT_COUNT * 2];
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uint32_t vcoeff[DC_VFILT_COUNT];
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uint32_t vp_coeff[VP_COEFF_SIZE / 4];
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#endif
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};
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static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
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{
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return (((xres * (bpp >> 3)) + 7) & ~7);
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}
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void lx_set_mode(struct fb_info *);
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unsigned int lx_framebuffer_size(void);
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int lx_blank_display(struct fb_info *, int);
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void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
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unsigned int, unsigned int);
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#ifdef CONFIG_PM
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int lx_powerdown(struct fb_info *info);
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int lx_powerup(struct fb_info *info);
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#endif
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/* Graphics Processor registers (table 6-29 from the data book) */
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enum gp_registers {
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GP_DST_OFFSET = 0,
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GP_SRC_OFFSET,
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GP_STRIDE,
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GP_WID_HEIGHT,
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GP_SRC_COLOR_FG,
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GP_SRC_COLOR_BG,
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GP_PAT_COLOR_0,
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GP_PAT_COLOR_1,
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GP_PAT_COLOR_2,
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GP_PAT_COLOR_3,
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GP_PAT_COLOR_4,
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GP_PAT_COLOR_5,
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GP_PAT_DATA_0,
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GP_PAT_DATA_1,
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GP_RASTER_MODE,
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GP_VECTOR_MODE,
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GP_BLT_MODE,
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GP_BLT_STATUS,
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GP_HST_SRC,
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GP_BASE_OFFSET,
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GP_CMD_TOP,
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GP_CMD_BOT,
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GP_CMD_READ,
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GP_CMD_WRITE,
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GP_CH3_OFFSET,
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GP_CH3_MODE_STR,
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GP_CH3_WIDHI,
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GP_CH3_HSRC,
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GP_LUT_INDEX,
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GP_LUT_DATA,
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GP_INT_CNTRL, /* 0x78 */
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};
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#define GP_BLT_STATUS_CE (1 << 4) /* cmd buf empty */
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#define GP_BLT_STATUS_PB (1 << 0) /* primative busy */
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/* Display Controller registers (table 6-47 from the data book) */
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enum dc_registers {
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DC_UNLOCK = 0,
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DC_GENERAL_CFG,
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DC_DISPLAY_CFG,
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DC_ARB_CFG,
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DC_FB_ST_OFFSET,
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DC_CB_ST_OFFSET,
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DC_CURS_ST_OFFSET,
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DC_RSVD_0,
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DC_VID_Y_ST_OFFSET,
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DC_VID_U_ST_OFFSET,
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DC_VID_V_ST_OFFSET,
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DC_DV_TOP,
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DC_LINE_SIZE,
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DC_GFX_PITCH,
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DC_VID_YUV_PITCH,
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DC_RSVD_1,
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DC_H_ACTIVE_TIMING,
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DC_H_BLANK_TIMING,
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DC_H_SYNC_TIMING,
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DC_RSVD_2,
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DC_V_ACTIVE_TIMING,
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DC_V_BLANK_TIMING,
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DC_V_SYNC_TIMING,
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DC_FB_ACTIVE,
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DC_CURSOR_X,
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DC_CURSOR_Y,
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DC_RSVD_3,
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DC_LINE_CNT,
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DC_PAL_ADDRESS,
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DC_PAL_DATA,
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DC_DFIFO_DIAG,
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DC_CFIFO_DIAG,
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DC_VID_DS_DELTA,
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DC_GLIU0_MEM_OFFSET,
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DC_DV_CTL,
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DC_DV_ACCESS,
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DC_GFX_SCALE,
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DC_IRQ_FILT_CTL,
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DC_FILT_COEFF1,
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DC_FILT_COEFF2,
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DC_VBI_EVEN_CTL,
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DC_VBI_ODD_CTL,
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DC_VBI_HOR,
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DC_VBI_LN_ODD,
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DC_VBI_LN_EVEN,
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DC_VBI_PITCH,
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DC_CLR_KEY,
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DC_CLR_KEY_MASK,
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DC_CLR_KEY_X,
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DC_CLR_KEY_Y,
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DC_IRQ,
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DC_RSVD_4,
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DC_RSVD_5,
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DC_GENLK_CTL,
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DC_VID_EVEN_Y_ST_OFFSET,
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DC_VID_EVEN_U_ST_OFFSET,
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DC_VID_EVEN_V_ST_OFFSET,
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DC_V_ACTIVE_EVEN_TIMING,
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DC_V_BLANK_EVEN_TIMING,
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DC_V_SYNC_EVEN_TIMING, /* 0xec */
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};
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#define DC_UNLOCK_LOCK 0x00000000
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#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
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#define DC_GENERAL_CFG_FDTY (1 << 17)
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#define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
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#define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
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#define DC_GENERAL_CFG_VGAE (1 << 7)
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#define DC_GENERAL_CFG_DECE (1 << 6)
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#define DC_GENERAL_CFG_CMPE (1 << 5)
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#define DC_GENERAL_CFG_VIDE (1 << 3)
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#define DC_GENERAL_CFG_DFLE (1 << 0)
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#define DC_DISPLAY_CFG_VISL (1 << 27)
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#define DC_DISPLAY_CFG_PALB (1 << 25)
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#define DC_DISPLAY_CFG_DCEN (1 << 24)
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#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
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#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
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#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
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#define DC_DISPLAY_CFG_TRUP (1 << 6)
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#define DC_DISPLAY_CFG_VDEN (1 << 4)
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#define DC_DISPLAY_CFG_GDEN (1 << 3)
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#define DC_DISPLAY_CFG_TGEN (1 << 0)
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#define DC_DV_TOP_DV_TOP_EN (1 << 0)
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#define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) | (1 << 11))
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#define DC_DV_CTL_DV_LINE_SIZE_1K (0)
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#define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
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#define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
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#define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) | (1 << 11))
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#define DC_DV_CTL_CLEAR_DV_RAM (1 << 0)
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#define DC_IRQ_FILT_CTL_H_FILT_SEL (1 << 10)
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#define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
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#define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21) /* undocumented? */
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#define DC_IRQ_STATUS (1 << 20) /* undocumented? */
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#define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK (1 << 1)
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#define DC_IRQ_MASK (1 << 0)
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#define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
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#define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
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#define DC_GENLK_CTL_FLICK_EN (1 << 24)
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#define DC_GENLK_CTL_GENLK_EN (1 << 18)
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/*
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* Video Processor registers (table 6-71).
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* There is space for 64 bit values, but we never use more than the
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* lower 32 bits. The actual register save/restore code only bothers
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* to restore those 32 bits.
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*/
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enum vp_registers {
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VP_VCFG = 0,
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VP_DCFG,
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VP_VX,
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VP_VY,
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VP_SCL,
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VP_VCK,
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VP_VCM,
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VP_PAR,
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VP_PDR,
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VP_SLR,
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VP_MISC,
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VP_CCS,
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VP_VYS,
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VP_VXS,
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VP_RSVD_0,
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VP_VDC,
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VP_RSVD_1,
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VP_CRC,
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VP_CRC32,
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VP_VDE,
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VP_CCK,
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VP_CCM,
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VP_CC1,
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VP_CC2,
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VP_A1X,
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VP_A1Y,
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VP_A1C,
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VP_A1T,
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VP_A2X,
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VP_A2Y,
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VP_A2C,
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VP_A2T,
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VP_A3X,
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VP_A3Y,
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VP_A3C,
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VP_A3T,
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VP_VRR,
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VP_AWT,
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VP_VTM,
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VP_VYE,
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VP_A1YE,
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VP_A2YE,
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VP_A3YE, /* 0x150 */
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VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
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};
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#define VP_VCFG_VID_EN (1 << 0)
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#define VP_DCFG_GV_GAM (1 << 21)
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#define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) | (1 << 18) | (1 << 19))
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#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */
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#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
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#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
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#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
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#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
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#define VP_DCFG_DAC_BL_EN (1 << 3)
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#define VP_DCFG_VSYNC_EN (1 << 2)
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#define VP_DCFG_HSYNC_EN (1 << 1)
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#define VP_DCFG_CRT_EN (1 << 0)
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#define VP_MISC_APWRDN (1 << 11)
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#define VP_MISC_DACPWRDN (1 << 10)
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#define VP_MISC_BYP_BOTH (1 << 0)
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/*
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* Flat Panel registers (table 6-71).
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* Also 64 bit registers; see above note about 32-bit handling.
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*/
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/* we're actually in the VP register space, starting at address 0x400 */
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#define VP_FP_START 0x400
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enum fp_registers {
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FP_PT1 = 0,
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FP_PT2,
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FP_PM,
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FP_DFC,
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FP_RSVD_0,
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FP_RSVD_1,
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FP_RSVD_2,
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FP_RSVD_3,
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FP_RSVD_4,
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FP_DCA,
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FP_DMD,
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FP_CRC, /* 0x458 */
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};
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#define FP_PT2_HSP (1 << 22)
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#define FP_PT2_VSP (1 << 23)
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#define FP_PT2_SCRC (1 << 27) /* shfclk free */
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#define FP_PM_P (1 << 24) /* panel power ctl */
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#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
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#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
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#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
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#define FP_PM_PANEL_ON (1 << 0) /* r/o */
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#define FP_DFC_BC ((1 << 4) | (1 << 5) | (1 << 6))
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/* register access functions */
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static inline uint32_t read_gp(struct lxfb_par *par, int reg)
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{
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return readl(par->gp_regs + 4*reg);
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}
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static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
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{
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writel(val, par->gp_regs + 4*reg);
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}
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static inline uint32_t read_dc(struct lxfb_par *par, int reg)
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{
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return readl(par->dc_regs + 4*reg);
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}
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static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
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{
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writel(val, par->dc_regs + 4*reg);
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}
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static inline uint32_t read_vp(struct lxfb_par *par, int reg)
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{
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return readl(par->vp_regs + 8*reg);
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}
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static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
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{
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writel(val, par->vp_regs + 8*reg);
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}
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static inline uint32_t read_fp(struct lxfb_par *par, int reg)
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{
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return readl(par->vp_regs + 8*reg + VP_FP_START);
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}
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static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
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{
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writel(val, par->vp_regs + 8*reg + VP_FP_START);
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}
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/* MSRs are defined in linux/cs5535.h; their bitfields are here */
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#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
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#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
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#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
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#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
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/* note: this is actually the VP's GLD_MSR_CONFIG */
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#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
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#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
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#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
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#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP *and* CRT */
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#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
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#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
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#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
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#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
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#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
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#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
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#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
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#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
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#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
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#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
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#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
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#endif
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