mirror of https://gitee.com/openkylin/linux.git
353 lines
10 KiB
C
353 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Genesys Logic, Inc.
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*
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* Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
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*
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* Version: v0.9.0 (2019-08-08)
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/pci.h>
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#include <linux/mmc/mmc.h>
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#include <linux/delay.h>
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#include "sdhci.h"
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#include "sdhci-pci.h"
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/* Genesys Logic extra registers */
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#define SDHCI_GLI_9750_WT 0x800
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#define SDHCI_GLI_9750_WT_EN BIT(0)
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#define GLI_9750_WT_EN_ON 0x1
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#define GLI_9750_WT_EN_OFF 0x0
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#define SDHCI_GLI_9750_DRIVING 0x860
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#define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
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#define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
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#define GLI_9750_DRIVING_1_VALUE 0xFFF
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#define GLI_9750_DRIVING_2_VALUE 0x3
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#define SDHCI_GLI_9750_PLL 0x864
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#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
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#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
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#define GLI_9750_PLL_TX2_INV_VALUE 0x1
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#define GLI_9750_PLL_TX2_DLY_VALUE 0x0
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#define SDHCI_GLI_9750_SW_CTRL 0x874
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#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
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#define GLI_9750_SW_CTRL_4_VALUE 0x3
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#define SDHCI_GLI_9750_MISC 0x878
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#define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
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#define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
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#define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
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#define GLI_9750_MISC_TX1_INV_VALUE 0x0
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#define GLI_9750_MISC_RX_INV_ON 0x1
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#define GLI_9750_MISC_RX_INV_OFF 0x0
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#define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
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#define GLI_9750_MISC_TX1_DLY_VALUE 0x5
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#define SDHCI_GLI_9750_TUNING_CONTROL 0x540
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#define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
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#define GLI_9750_TUNING_CONTROL_EN_ON 0x1
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#define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
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#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
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#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
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#define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
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#define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
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#define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
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#define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
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#define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
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#define GLI_MAX_TUNING_LOOP 40
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/* Genesys Logic chipset */
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static inline void gl9750_wt_on(struct sdhci_host *host)
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{
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u32 wt_value;
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u32 wt_enable;
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wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
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wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
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if (wt_enable == GLI_9750_WT_EN_ON)
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return;
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wt_value &= ~SDHCI_GLI_9750_WT_EN;
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wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
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sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
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}
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static inline void gl9750_wt_off(struct sdhci_host *host)
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{
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u32 wt_value;
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u32 wt_enable;
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wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
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wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
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if (wt_enable == GLI_9750_WT_EN_OFF)
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return;
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wt_value &= ~SDHCI_GLI_9750_WT_EN;
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wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
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sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
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}
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static void gli_set_9750(struct sdhci_host *host)
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{
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u32 driving_value;
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u32 pll_value;
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u32 sw_ctrl_value;
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u32 misc_value;
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u32 parameter_value;
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u32 control_value;
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u16 ctrl2;
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gl9750_wt_on(host);
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driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
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pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
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sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
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misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
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parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
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control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
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driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
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driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
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driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
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GLI_9750_DRIVING_1_VALUE);
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driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
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GLI_9750_DRIVING_2_VALUE);
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sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
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sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
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sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
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GLI_9750_SW_CTRL_4_VALUE);
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sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
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/* reset the tuning flow after reinit and before starting tuning */
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pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
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pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
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pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
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GLI_9750_PLL_TX2_INV_VALUE);
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pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
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GLI_9750_PLL_TX2_DLY_VALUE);
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misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
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misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
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misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
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misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
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GLI_9750_MISC_TX1_INV_VALUE);
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misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
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GLI_9750_MISC_RX_INV_VALUE);
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misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
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GLI_9750_MISC_TX1_DLY_VALUE);
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parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
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parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
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GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
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control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
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control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
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control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
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GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
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control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
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GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
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sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
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sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
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/* disable tuned clk */
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ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
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sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
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/* enable tuning parameters control */
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control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
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control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
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GLI_9750_TUNING_CONTROL_EN_ON);
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sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
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/* write tuning parameters */
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sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
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/* disable tuning parameters control */
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control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
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control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
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GLI_9750_TUNING_CONTROL_EN_OFF);
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sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
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/* clear tuned clk */
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ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
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sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
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gl9750_wt_off(host);
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}
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static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
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{
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u32 misc_value;
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gl9750_wt_on(host);
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misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
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misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
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if (b) {
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misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
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GLI_9750_MISC_RX_INV_ON);
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} else {
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misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
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GLI_9750_MISC_RX_INV_OFF);
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}
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sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
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gl9750_wt_off(host);
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}
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static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
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{
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int i;
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int rx_inv;
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for (rx_inv = 0; rx_inv < 2; rx_inv++) {
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gli_set_9750_rx_inv(host, !!rx_inv);
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sdhci_start_tuning(host);
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for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
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u16 ctrl;
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sdhci_send_tuning(host, opcode);
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if (!host->tuning_done) {
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sdhci_abort_tuning(host, opcode);
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break;
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}
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
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if (ctrl & SDHCI_CTRL_TUNED_CLK)
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return 0; /* Success! */
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break;
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}
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}
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}
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if (!host->tuning_done) {
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pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
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mmc_hostname(host->mmc));
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return -ETIMEDOUT;
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}
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pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
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mmc_hostname(host->mmc));
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sdhci_reset_tuning(host);
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return -EAGAIN;
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}
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static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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host->mmc->retune_period = 0;
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if (host->tuning_mode == SDHCI_TUNING_MODE_1)
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host->mmc->retune_period = host->tuning_count;
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gli_set_9750(host);
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host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
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sdhci_end_tuning(host);
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return 0;
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}
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static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
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{
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struct sdhci_host *host = slot->host;
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slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
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sdhci_enable_v4_mode(host);
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return 0;
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}
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static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
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{
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struct sdhci_host *host = slot->host;
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slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
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sdhci_enable_v4_mode(host);
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return 0;
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}
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static void sdhci_gli_voltage_switch(struct sdhci_host *host)
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{
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/*
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* According to Section 3.6.1 signal voltage switch procedure in
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* SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
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* follows:
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* (6) Set 1.8V Signal Enable in the Host Control 2 register.
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* (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
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* period.
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* (8) If 1.8V Signal Enable is cleared by Host Controller, go to
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* step (12).
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*
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* Wait 5ms after set 1.8V signal enable in Host Control 2 register
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* to ensure 1.8V signal enable bit is set by GL9750/GL9755.
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*/
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usleep_range(5000, 5500);
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}
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static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
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{
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sdhci_reset(host, mask);
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gli_set_9750(host);
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}
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static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
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{
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u32 value;
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value = readl(host->ioaddr + reg);
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if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
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value |= 0xc8;
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return value;
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}
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static const struct sdhci_ops sdhci_gl9755_ops = {
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.set_clock = sdhci_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.voltage_switch = sdhci_gli_voltage_switch,
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};
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const struct sdhci_pci_fixes sdhci_gl9755 = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
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.probe_slot = gli_probe_slot_gl9755,
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.ops = &sdhci_gl9755_ops,
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};
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static const struct sdhci_ops sdhci_gl9750_ops = {
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.read_l = sdhci_gl9750_readl,
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.set_clock = sdhci_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_gl9750_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.voltage_switch = sdhci_gli_voltage_switch,
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.platform_execute_tuning = gl9750_execute_tuning,
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};
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const struct sdhci_pci_fixes sdhci_gl9750 = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
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.probe_slot = gli_probe_slot_gl9750,
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.ops = &sdhci_gl9750_ops,
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};
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