mirror of https://gitee.com/openkylin/linux.git
284 lines
7.7 KiB
C
284 lines
7.7 KiB
C
/*
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* Copyright © 2006-2010 Intel Corporation
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Dave Airlie <airlied@linux.ie>
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* Jesse Barnes <jesse.barnes@intel.com>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*/
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#include "intel_drv.h"
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#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
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void
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intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
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struct drm_display_mode *adjusted_mode)
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{
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adjusted_mode->hdisplay = fixed_mode->hdisplay;
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adjusted_mode->hsync_start = fixed_mode->hsync_start;
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adjusted_mode->hsync_end = fixed_mode->hsync_end;
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adjusted_mode->htotal = fixed_mode->htotal;
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adjusted_mode->vdisplay = fixed_mode->vdisplay;
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adjusted_mode->vsync_start = fixed_mode->vsync_start;
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adjusted_mode->vsync_end = fixed_mode->vsync_end;
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adjusted_mode->vtotal = fixed_mode->vtotal;
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adjusted_mode->clock = fixed_mode->clock;
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drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
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}
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/* adjusted_mode has been preset to be the panel's fixed mode */
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void
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intel_pch_panel_fitting(struct drm_device *dev,
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int fitting_mode,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int x, y, width, height;
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x = y = width = height = 0;
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/* Native modes don't need fitting */
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if (adjusted_mode->hdisplay == mode->hdisplay &&
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adjusted_mode->vdisplay == mode->vdisplay)
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goto done;
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switch (fitting_mode) {
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case DRM_MODE_SCALE_CENTER:
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width = mode->hdisplay;
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height = mode->vdisplay;
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x = (adjusted_mode->hdisplay - width + 1)/2;
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y = (adjusted_mode->vdisplay - height + 1)/2;
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break;
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case DRM_MODE_SCALE_ASPECT:
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/* Scale but preserve the aspect ratio */
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{
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u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
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u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
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if (scaled_width > scaled_height) { /* pillar */
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width = scaled_height / mode->vdisplay;
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x = (adjusted_mode->hdisplay - width + 1) / 2;
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y = 0;
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height = adjusted_mode->vdisplay;
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} else if (scaled_width < scaled_height) { /* letter */
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height = scaled_width / mode->hdisplay;
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y = (adjusted_mode->vdisplay - height + 1) / 2;
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x = 0;
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width = adjusted_mode->hdisplay;
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} else {
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x = y = 0;
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width = adjusted_mode->hdisplay;
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height = adjusted_mode->vdisplay;
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}
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}
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break;
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default:
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case DRM_MODE_SCALE_FULLSCREEN:
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x = y = 0;
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width = adjusted_mode->hdisplay;
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height = adjusted_mode->vdisplay;
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break;
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}
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done:
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dev_priv->pch_pf_pos = (x << 16) | y;
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dev_priv->pch_pf_size = (width << 16) | height;
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}
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static int is_backlight_combination_mode(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (INTEL_INFO(dev)->gen >= 4)
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return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
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if (IS_GEN2(dev))
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return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
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return 0;
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}
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static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
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{
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u32 val;
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/* Restore the CTL value if it lost, e.g. GPU reset */
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if (HAS_PCH_SPLIT(dev_priv->dev)) {
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val = I915_READ(BLC_PWM_PCH_CTL2);
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if (dev_priv->saveBLC_PWM_CTL2 == 0) {
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dev_priv->saveBLC_PWM_CTL2 = val;
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} else if (val == 0) {
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I915_WRITE(BLC_PWM_PCH_CTL2,
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dev_priv->saveBLC_PWM_CTL);
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val = dev_priv->saveBLC_PWM_CTL;
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}
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} else {
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val = I915_READ(BLC_PWM_CTL);
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if (dev_priv->saveBLC_PWM_CTL == 0) {
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dev_priv->saveBLC_PWM_CTL = val;
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dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
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} else if (val == 0) {
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I915_WRITE(BLC_PWM_CTL,
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dev_priv->saveBLC_PWM_CTL);
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I915_WRITE(BLC_PWM_CTL2,
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dev_priv->saveBLC_PWM_CTL2);
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val = dev_priv->saveBLC_PWM_CTL;
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}
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}
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return val;
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}
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u32 intel_panel_get_max_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 max;
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max = i915_read_blc_pwm_ctl(dev_priv);
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if (max == 0) {
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/* XXX add code here to query mode clock or hardware clock
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* and program max PWM appropriately.
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*/
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printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
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return 1;
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}
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if (HAS_PCH_SPLIT(dev)) {
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max >>= 16;
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} else {
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if (IS_PINEVIEW(dev)) {
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max >>= 17;
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} else {
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max >>= 16;
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if (INTEL_INFO(dev)->gen < 4)
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max &= ~1;
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}
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if (is_backlight_combination_mode(dev))
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max *= 0xff;
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}
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DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
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return max;
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}
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u32 intel_panel_get_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val;
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if (HAS_PCH_SPLIT(dev)) {
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val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
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} else {
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val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
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if (IS_PINEVIEW(dev))
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val >>= 1;
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if (is_backlight_combination_mode(dev)){
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u8 lbpc;
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val &= ~1;
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pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
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val *= lbpc;
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val >>= 1;
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}
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}
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DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
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return val;
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}
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static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
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I915_WRITE(BLC_PWM_CPU_CTL, val | level);
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}
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void intel_panel_set_backlight(struct drm_device *dev, u32 level)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 tmp;
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DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
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if (HAS_PCH_SPLIT(dev))
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return intel_pch_panel_set_backlight(dev, level);
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if (is_backlight_combination_mode(dev)){
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u32 max = intel_panel_get_max_backlight(dev);
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u8 lpbc;
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lpbc = level * 0xfe / max + 1;
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level /= lpbc;
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pci_write_config_byte(dev->pdev, PCI_LBPC, lpbc);
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}
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tmp = I915_READ(BLC_PWM_CTL);
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if (IS_PINEVIEW(dev)) {
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tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
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level <<= 1;
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} else
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tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
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I915_WRITE(BLC_PWM_CTL, tmp | level);
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}
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void intel_panel_disable_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->backlight_enabled) {
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dev_priv->backlight_level = intel_panel_get_backlight(dev);
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dev_priv->backlight_enabled = false;
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}
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intel_panel_set_backlight(dev, 0);
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}
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void intel_panel_enable_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->backlight_level == 0)
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dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
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intel_panel_set_backlight(dev, dev_priv->backlight_level);
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dev_priv->backlight_enabled = true;
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}
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void intel_panel_setup_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->backlight_level = intel_panel_get_backlight(dev);
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dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
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}
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