mirror of https://gitee.com/openkylin/linux.git
195 lines
5.1 KiB
ArmAsm
195 lines
5.1 KiB
ArmAsm
/* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
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*
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* Copyright (C) 1995, 1997, 2005 David S. Miller <davem@davemloft.net>
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* Copyright (C) 1996 Eddie C. Dost (ecd@brainaid.de)
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* Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <linux/config.h>
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#include <asm/head.h>
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#include <asm/asi.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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.text
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.align 32
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/*
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* On a second level vpte miss, check whether the original fault is to the OBP
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* range (note that this is only possible for instruction miss, data misses to
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* obp range do not use vpte). If so, go back directly to the faulting address.
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* This is because we want to read the tpc, otherwise we have no way of knowing
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* the 8k aligned faulting address if we are using >8k kernel pagesize. This
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* also ensures no vpte range addresses are dropped into tlb while obp is
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* executing (see inherit_locked_prom_mappings() rant).
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*/
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sparc64_vpte_nucleus:
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/* Note that kvmap below has verified that the address is
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* in the range MODULES_VADDR --> VMALLOC_END already. So
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* here we need only check if it is an OBP address or not.
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*/
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sethi %hi(LOW_OBP_ADDRESS), %g5
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cmp %g4, %g5
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blu,pn %xcc, kern_vpte
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mov 0x1, %g5
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sllx %g5, 32, %g5
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cmp %g4, %g5
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blu,pn %xcc, vpte_insn_obp
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nop
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/* These two instructions are patched by paginig_init(). */
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kern_vpte:
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sethi %hi(swapper_pgd_zero), %g5
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lduw [%g5 + %lo(swapper_pgd_zero)], %g5
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/* With kernel PGD in %g5, branch back into dtlb_backend. */
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ba,pt %xcc, sparc64_kpte_continue
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andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */
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vpte_noent:
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/* Restore previous TAG_ACCESS, %g5 is zero, and we will
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* skip over the trap instruction so that the top level
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* TLB miss handler will thing this %g5 value is just an
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* invalid PTE, thus branching to full fault processing.
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*/
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mov TLB_SFSR, %g1
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stxa %g4, [%g1 + %g1] ASI_DMMU
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done
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vpte_insn_obp:
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/* Behave as if we are at TL0. */
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wrpr %g0, 1, %tl
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rdpr %tpc, %g4 /* Find original faulting iaddr */
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srlx %g4, 13, %g4 /* Throw out context bits */
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sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */
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/* Restore previous TAG_ACCESS. */
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mov TLB_SFSR, %g1
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stxa %g4, [%g1 + %g1] ASI_IMMU
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sethi %hi(prom_trans), %g5
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or %g5, %lo(prom_trans), %g5
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1: ldx [%g5 + 0x00], %g6 ! base
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brz,a,pn %g6, longpath ! no more entries, fail
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mov TLB_SFSR, %g1 ! and restore %g1
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ldx [%g5 + 0x08], %g1 ! len
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add %g6, %g1, %g1 ! end
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cmp %g6, %g4
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bgu,pt %xcc, 2f
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cmp %g4, %g1
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bgeu,pt %xcc, 2f
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ldx [%g5 + 0x10], %g1 ! PTE
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/* TLB load, restore %g1, and return from trap. */
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sub %g4, %g6, %g6
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add %g1, %g6, %g5
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mov TLB_SFSR, %g1
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stxa %g5, [%g0] ASI_ITLB_DATA_IN
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retry
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2: ba,pt %xcc, 1b
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add %g5, (3 * 8), %g5 ! next entry
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kvmap_do_obp:
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sethi %hi(prom_trans), %g5
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or %g5, %lo(prom_trans), %g5
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srlx %g4, 13, %g4
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sllx %g4, 13, %g4
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1: ldx [%g5 + 0x00], %g6 ! base
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brz,a,pn %g6, longpath ! no more entries, fail
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mov TLB_SFSR, %g1 ! and restore %g1
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ldx [%g5 + 0x08], %g1 ! len
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add %g6, %g1, %g1 ! end
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cmp %g6, %g4
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bgu,pt %xcc, 2f
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cmp %g4, %g1
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bgeu,pt %xcc, 2f
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ldx [%g5 + 0x10], %g1 ! PTE
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/* TLB load, restore %g1, and return from trap. */
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sub %g4, %g6, %g6
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add %g1, %g6, %g5
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mov TLB_SFSR, %g1
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stxa %g5, [%g0] ASI_DTLB_DATA_IN
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retry
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2: ba,pt %xcc, 1b
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add %g5, (3 * 8), %g5 ! next entry
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/*
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* On a first level data miss, check whether this is to the OBP range (note
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* that such accesses can be made by prom, as well as by kernel using
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* prom_getproperty on "address"), and if so, do not use vpte access ...
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* rather, use information saved during inherit_prom_mappings() using 8k
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* pagesize.
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*/
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.align 32
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kvmap:
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brgez,pn %g4, kvmap_nonlinear
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nop
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#ifdef CONFIG_DEBUG_PAGEALLOC
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.globl kvmap_linear_patch
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kvmap_linear_patch:
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#endif
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ba,pt %xcc, kvmap_load
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xor %g2, %g4, %g5
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#ifdef CONFIG_DEBUG_PAGEALLOC
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sethi %hi(swapper_pg_dir), %g5
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or %g5, %lo(swapper_pg_dir), %g5
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sllx %g4, 64 - (PGDIR_SHIFT + PGDIR_BITS), %g6
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srlx %g6, 64 - PAGE_SHIFT, %g6
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andn %g6, 0x3, %g6
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lduw [%g5 + %g6], %g5
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brz,pn %g5, longpath
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sllx %g4, 64 - (PMD_SHIFT + PMD_BITS), %g6
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srlx %g6, 64 - PAGE_SHIFT, %g6
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sllx %g5, 11, %g5
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andn %g6, 0x3, %g6
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lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
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brz,pn %g5, longpath
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sllx %g4, 64 - PMD_SHIFT, %g6
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srlx %g6, 64 - PAGE_SHIFT, %g6
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sllx %g5, 11, %g5
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andn %g6, 0x7, %g6
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ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
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brz,pn %g5, longpath
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nop
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ba,a,pt %xcc, kvmap_load
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#endif
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kvmap_nonlinear:
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sethi %hi(MODULES_VADDR), %g5
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cmp %g4, %g5
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blu,pn %xcc, longpath
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mov (VMALLOC_END >> 24), %g5
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sllx %g5, 24, %g5
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cmp %g4, %g5
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bgeu,pn %xcc, longpath
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nop
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kvmap_check_obp:
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sethi %hi(LOW_OBP_ADDRESS), %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_vmalloc_addr
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mov 0x1, %g5
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sllx %g5, 32, %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_do_obp
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nop
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kvmap_vmalloc_addr:
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/* If we get here, a vmalloc addr was accessed, load kernel VPTE. */
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ldxa [%g3 + %g6] ASI_N, %g5
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brgez,pn %g5, longpath
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nop
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kvmap_load:
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/* PTE is valid, load into TLB and return from trap. */
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stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
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retry
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