mirror of https://gitee.com/openkylin/linux.git
514 lines
14 KiB
C
514 lines
14 KiB
C
/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include "qed.h"
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#include <linux/qed/qed_chain.h>
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#include "qed_cxt.h"
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#include "qed_dcbx.h"
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#include "qed_hsi.h"
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#include "qed_hw.h"
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#include "qed_int.h"
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#include "qed_reg_addr.h"
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#include "qed_sp.h"
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#include "qed_sriov.h"
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int qed_sp_init_request(struct qed_hwfn *p_hwfn,
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struct qed_spq_entry **pp_ent,
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u8 cmd,
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u8 protocol,
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struct qed_sp_init_data *p_data)
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{
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u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
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struct qed_spq_entry *p_ent = NULL;
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int rc;
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if (!pp_ent)
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return -ENOMEM;
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rc = qed_spq_get_entry(p_hwfn, pp_ent);
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if (rc != 0)
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return rc;
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p_ent = *pp_ent;
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p_ent->elem.hdr.cid = cpu_to_le32(opaque_cid);
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p_ent->elem.hdr.cmd_id = cmd;
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p_ent->elem.hdr.protocol_id = protocol;
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p_ent->priority = QED_SPQ_PRIORITY_NORMAL;
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p_ent->comp_mode = p_data->comp_mode;
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p_ent->comp_done.done = 0;
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switch (p_ent->comp_mode) {
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case QED_SPQ_MODE_EBLOCK:
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p_ent->comp_cb.cookie = &p_ent->comp_done;
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break;
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case QED_SPQ_MODE_BLOCK:
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if (!p_data->p_comp_data)
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return -EINVAL;
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p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
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break;
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case QED_SPQ_MODE_CB:
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if (!p_data->p_comp_data)
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p_ent->comp_cb.function = NULL;
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else
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p_ent->comp_cb = *p_data->p_comp_data;
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break;
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default:
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DP_NOTICE(p_hwfn, "Unknown SPQE completion mode %d\n",
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p_ent->comp_mode);
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return -EINVAL;
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}
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DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
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"Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
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opaque_cid, cmd, protocol,
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(unsigned long)&p_ent->ramrod,
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D_TRINE(p_ent->comp_mode, QED_SPQ_MODE_EBLOCK,
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QED_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
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"MODE_CB"));
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memset(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
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return 0;
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}
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static enum tunnel_clss qed_tunn_get_clss_type(u8 type)
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{
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switch (type) {
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case QED_TUNN_CLSS_MAC_VLAN:
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return TUNNEL_CLSS_MAC_VLAN;
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case QED_TUNN_CLSS_MAC_VNI:
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return TUNNEL_CLSS_MAC_VNI;
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case QED_TUNN_CLSS_INNER_MAC_VLAN:
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return TUNNEL_CLSS_INNER_MAC_VLAN;
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case QED_TUNN_CLSS_INNER_MAC_VNI:
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return TUNNEL_CLSS_INNER_MAC_VNI;
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default:
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return TUNNEL_CLSS_MAC_VLAN;
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}
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}
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static void
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qed_tunn_set_pf_fix_tunn_mode(struct qed_hwfn *p_hwfn,
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struct qed_tunn_update_params *p_src,
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struct pf_update_tunnel_config *p_tunn_cfg)
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{
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unsigned long cached_tunn_mode = p_hwfn->cdev->tunn_mode;
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unsigned long update_mask = p_src->tunn_mode_update_mask;
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unsigned long tunn_mode = p_src->tunn_mode;
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unsigned long new_tunn_mode = 0;
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if (test_bit(QED_MODE_L2GRE_TUNN, &update_mask)) {
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if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
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__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
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} else {
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if (test_bit(QED_MODE_L2GRE_TUNN, &cached_tunn_mode))
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__set_bit(QED_MODE_L2GRE_TUNN, &new_tunn_mode);
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}
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if (test_bit(QED_MODE_IPGRE_TUNN, &update_mask)) {
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if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
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__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
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} else {
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if (test_bit(QED_MODE_IPGRE_TUNN, &cached_tunn_mode))
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__set_bit(QED_MODE_IPGRE_TUNN, &new_tunn_mode);
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}
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if (test_bit(QED_MODE_VXLAN_TUNN, &update_mask)) {
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if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
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__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
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} else {
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if (test_bit(QED_MODE_VXLAN_TUNN, &cached_tunn_mode))
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__set_bit(QED_MODE_VXLAN_TUNN, &new_tunn_mode);
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}
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if (p_src->update_geneve_udp_port) {
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p_tunn_cfg->set_geneve_udp_port_flg = 1;
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p_tunn_cfg->geneve_udp_port =
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cpu_to_le16(p_src->geneve_udp_port);
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}
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if (test_bit(QED_MODE_L2GENEVE_TUNN, &update_mask)) {
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if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
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__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
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} else {
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if (test_bit(QED_MODE_L2GENEVE_TUNN, &cached_tunn_mode))
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__set_bit(QED_MODE_L2GENEVE_TUNN, &new_tunn_mode);
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}
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if (test_bit(QED_MODE_IPGENEVE_TUNN, &update_mask)) {
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if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
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__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
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} else {
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if (test_bit(QED_MODE_IPGENEVE_TUNN, &cached_tunn_mode))
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__set_bit(QED_MODE_IPGENEVE_TUNN, &new_tunn_mode);
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}
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p_src->tunn_mode = new_tunn_mode;
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}
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static void
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qed_tunn_set_pf_update_params(struct qed_hwfn *p_hwfn,
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struct qed_tunn_update_params *p_src,
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struct pf_update_tunnel_config *p_tunn_cfg)
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{
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unsigned long tunn_mode = p_src->tunn_mode;
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enum tunnel_clss type;
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qed_tunn_set_pf_fix_tunn_mode(p_hwfn, p_src, p_tunn_cfg);
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p_tunn_cfg->update_rx_pf_clss = p_src->update_rx_pf_clss;
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p_tunn_cfg->update_tx_pf_clss = p_src->update_tx_pf_clss;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
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p_tunn_cfg->tunnel_clss_vxlan = type;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
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p_tunn_cfg->tunnel_clss_l2gre = type;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
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p_tunn_cfg->tunnel_clss_ipgre = type;
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if (p_src->update_vxlan_udp_port) {
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p_tunn_cfg->set_vxlan_udp_port_flg = 1;
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p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
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}
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if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_l2gre = 1;
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if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_ipgre = 1;
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if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_vxlan = 1;
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if (p_src->update_geneve_udp_port) {
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p_tunn_cfg->set_geneve_udp_port_flg = 1;
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p_tunn_cfg->geneve_udp_port =
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cpu_to_le16(p_src->geneve_udp_port);
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}
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if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_l2geneve = 1;
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if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_ipgeneve = 1;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
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p_tunn_cfg->tunnel_clss_l2geneve = type;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
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p_tunn_cfg->tunnel_clss_ipgeneve = type;
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}
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static void qed_set_hw_tunn_mode(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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unsigned long tunn_mode)
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{
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u8 l2gre_enable = 0, ipgre_enable = 0, vxlan_enable = 0;
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u8 l2geneve_enable = 0, ipgeneve_enable = 0;
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if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
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l2gre_enable = 1;
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if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
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ipgre_enable = 1;
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if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
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vxlan_enable = 1;
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qed_set_gre_enable(p_hwfn, p_ptt, l2gre_enable, ipgre_enable);
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qed_set_vxlan_enable(p_hwfn, p_ptt, vxlan_enable);
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if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
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l2geneve_enable = 1;
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if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
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ipgeneve_enable = 1;
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qed_set_geneve_enable(p_hwfn, p_ptt, l2geneve_enable,
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ipgeneve_enable);
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}
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static void
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qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
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struct qed_tunn_start_params *p_src,
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struct pf_start_tunnel_config *p_tunn_cfg)
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{
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unsigned long tunn_mode;
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enum tunnel_clss type;
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if (!p_src)
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return;
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tunn_mode = p_src->tunn_mode;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_vxlan);
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p_tunn_cfg->tunnel_clss_vxlan = type;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_l2gre);
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p_tunn_cfg->tunnel_clss_l2gre = type;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgre);
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p_tunn_cfg->tunnel_clss_ipgre = type;
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if (p_src->update_vxlan_udp_port) {
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p_tunn_cfg->set_vxlan_udp_port_flg = 1;
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p_tunn_cfg->vxlan_udp_port = cpu_to_le16(p_src->vxlan_udp_port);
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}
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if (test_bit(QED_MODE_L2GRE_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_l2gre = 1;
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if (test_bit(QED_MODE_IPGRE_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_ipgre = 1;
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if (test_bit(QED_MODE_VXLAN_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_vxlan = 1;
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if (p_src->update_geneve_udp_port) {
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p_tunn_cfg->set_geneve_udp_port_flg = 1;
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p_tunn_cfg->geneve_udp_port =
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cpu_to_le16(p_src->geneve_udp_port);
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}
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if (test_bit(QED_MODE_L2GENEVE_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_l2geneve = 1;
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if (test_bit(QED_MODE_IPGENEVE_TUNN, &tunn_mode))
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p_tunn_cfg->tx_enable_ipgeneve = 1;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_l2geneve);
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p_tunn_cfg->tunnel_clss_l2geneve = type;
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type = qed_tunn_get_clss_type(p_src->tunn_clss_ipgeneve);
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p_tunn_cfg->tunnel_clss_ipgeneve = type;
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}
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int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
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struct qed_tunn_start_params *p_tunn,
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enum qed_mf_mode mode, bool allow_npar_tx_switch)
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{
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struct pf_start_ramrod_data *p_ramrod = NULL;
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u16 sb = qed_int_get_sp_sb_id(p_hwfn);
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u8 sb_index = p_hwfn->p_eq->eq_sb_index;
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struct qed_spq_entry *p_ent = NULL;
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struct qed_sp_init_data init_data;
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int rc = -EINVAL;
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u8 page_cnt;
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/* update initial eq producer */
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qed_eq_prod_update(p_hwfn,
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qed_chain_get_prod_idx(&p_hwfn->p_eq->chain));
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memset(&init_data, 0, sizeof(init_data));
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init_data.cid = qed_spq_get_cid(p_hwfn);
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init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
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init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
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rc = qed_sp_init_request(p_hwfn, &p_ent,
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COMMON_RAMROD_PF_START,
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PROTOCOLID_COMMON,
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&init_data);
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if (rc)
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return rc;
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p_ramrod = &p_ent->ramrod.pf_start;
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p_ramrod->event_ring_sb_id = cpu_to_le16(sb);
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p_ramrod->event_ring_sb_index = sb_index;
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p_ramrod->path_id = QED_PATH_ID(p_hwfn);
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p_ramrod->dont_log_ramrods = 0;
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p_ramrod->log_type_mask = cpu_to_le16(0xf);
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switch (mode) {
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case QED_MF_DEFAULT:
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case QED_MF_NPAR:
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p_ramrod->mf_mode = MF_NPAR;
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break;
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case QED_MF_OVLAN:
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p_ramrod->mf_mode = MF_OVLAN;
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break;
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default:
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DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
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p_ramrod->mf_mode = MF_NPAR;
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}
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p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
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/* Place EQ address in RAMROD */
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DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
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p_hwfn->p_eq->chain.pbl.p_phys_table);
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page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
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p_ramrod->event_ring_num_pages = page_cnt;
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DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
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p_hwfn->p_consq->chain.pbl.p_phys_table);
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qed_tunn_set_pf_start_params(p_hwfn, p_tunn,
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&p_ramrod->tunnel_config);
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if (IS_MF_SI(p_hwfn))
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p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
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switch (p_hwfn->hw_info.personality) {
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case QED_PCI_ETH:
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p_ramrod->personality = PERSONALITY_ETH;
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break;
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case QED_PCI_ISCSI:
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p_ramrod->personality = PERSONALITY_ISCSI;
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break;
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case QED_PCI_ETH_ROCE:
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p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
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break;
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default:
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DP_NOTICE(p_hwfn, "Unkown personality %d\n",
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p_hwfn->hw_info.personality);
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p_ramrod->personality = PERSONALITY_ETH;
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}
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if (p_hwfn->cdev->p_iov_info) {
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struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
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p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
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p_ramrod->num_vfs = (u8) p_iov->total_vfs;
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}
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p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
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p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
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DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
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"Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
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sb, sb_index,
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p_ramrod->outer_tag);
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rc = qed_spq_post(p_hwfn, p_ent, NULL);
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if (p_tunn) {
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qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
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p_tunn->tunn_mode);
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p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
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}
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return rc;
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}
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int qed_sp_pf_update(struct qed_hwfn *p_hwfn)
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{
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struct qed_spq_entry *p_ent = NULL;
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struct qed_sp_init_data init_data;
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int rc = -EINVAL;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = QED_SPQ_MODE_CB;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
qed_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
|
|
&p_ent->ramrod.pf_update);
|
|
|
|
return qed_spq_post(p_hwfn, p_ent, NULL);
|
|
}
|
|
|
|
/* Set pf update ramrod command params */
|
|
int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
|
|
struct qed_tunn_update_params *p_tunn,
|
|
enum spq_mode comp_mode,
|
|
struct qed_spq_comp_cb *p_comp_data)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc = -EINVAL;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = comp_mode;
|
|
init_data.p_comp_data = p_comp_data;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
qed_tunn_set_pf_update_params(p_hwfn, p_tunn,
|
|
&p_ent->ramrod.pf_update.tunnel_config);
|
|
|
|
rc = qed_spq_post(p_hwfn, p_ent, NULL);
|
|
if (rc)
|
|
return rc;
|
|
|
|
if (p_tunn->update_vxlan_udp_port)
|
|
qed_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
|
|
p_tunn->vxlan_udp_port);
|
|
if (p_tunn->update_geneve_udp_port)
|
|
qed_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
|
|
p_tunn->geneve_udp_port);
|
|
|
|
qed_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
|
|
p_hwfn->cdev->tunn_mode = p_tunn->tunn_mode;
|
|
|
|
return rc;
|
|
}
|
|
|
|
int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc = -EINVAL;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
return qed_spq_post(p_hwfn, p_ent, NULL);
|
|
}
|
|
|
|
int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
|
|
{
|
|
struct qed_spq_entry *p_ent = NULL;
|
|
struct qed_sp_init_data init_data;
|
|
int rc;
|
|
|
|
/* Get SPQ entry */
|
|
memset(&init_data, 0, sizeof(init_data));
|
|
init_data.cid = qed_spq_get_cid(p_hwfn);
|
|
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
|
|
init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
|
|
|
|
rc = qed_sp_init_request(p_hwfn, &p_ent,
|
|
COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
|
|
&init_data);
|
|
if (rc)
|
|
return rc;
|
|
|
|
return qed_spq_post(p_hwfn, p_ent, NULL);
|
|
}
|