mirror of https://gitee.com/openkylin/linux.git
440 lines
15 KiB
C
440 lines
15 KiB
C
/*
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* This file contains defines, structures, etc. that are used
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* to communicate between kernel and user code.
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*/
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#ifndef _LINUX__HFI1_USER_H
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#define _LINUX__HFI1_USER_H
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#include <linux/types.h>
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/*
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* This version number is given to the driver by the user code during
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* initialization in the spu_userversion field of hfi1_user_info, so
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* the driver can check for compatibility with user code.
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*
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* The major version changes when data structures change in an incompatible
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* way. The driver must be the same for initialization to succeed.
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*/
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#define HFI1_USER_SWMAJOR 6
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/*
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* Minor version differences are always compatible
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* a within a major version, however if user software is larger
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* than driver software, some new features and/or structure fields
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* may not be implemented; the user code must deal with this if it
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* cares, or it must abort after initialization reports the difference.
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*/
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#define HFI1_USER_SWMINOR 1
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/*
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* We will encode the major/minor inside a single 32bit version number.
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*/
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#define HFI1_SWMAJOR_SHIFT 16
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/*
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* Set of HW and driver capability/feature bits.
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* These bit values are used to configure enabled/disabled HW and
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* driver features. The same set of bits are communicated to user
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* space.
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*/
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#define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */
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#define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */
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#define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */
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#define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */
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#define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */
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/* 1UL << 5 unused */
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#define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */
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#define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/
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#define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */
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#define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */
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#define HFI1_CAP_TID_UNMAP (1UL << 10) /* Disable Expected TID caching */
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#define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */
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#define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */
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#define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */
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#define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */
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#define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */
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/* 1UL << 16 unused */
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#define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */
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#define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */
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#define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0)
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#define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1)
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#define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2)
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/* User commands. */
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#define HFI1_CMD_ASSIGN_CTXT 1 /* allocate HFI and context */
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#define HFI1_CMD_CTXT_INFO 2 /* find out what resources we got */
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#define HFI1_CMD_USER_INFO 3 /* set up userspace */
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#define HFI1_CMD_TID_UPDATE 4 /* update expected TID entries */
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#define HFI1_CMD_TID_FREE 5 /* free expected TID entries */
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#define HFI1_CMD_CREDIT_UPD 6 /* force an update of PIO credit */
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#define HFI1_CMD_RECV_CTRL 8 /* control receipt of packets */
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#define HFI1_CMD_POLL_TYPE 9 /* set the kind of polling we want */
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#define HFI1_CMD_ACK_EVENT 10 /* ack & clear user status bits */
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#define HFI1_CMD_SET_PKEY 11 /* set context's pkey */
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#define HFI1_CMD_CTXT_RESET 12 /* reset context's HW send context */
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#define HFI1_CMD_TID_INVAL_READ 13 /* read TID cache invalidations */
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#define HFI1_CMD_GET_VERS 14 /* get the version of the user cdev */
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/*
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* User IOCTLs can not go above 128 if they do then see common.h and change the
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* base for the snoop ioctl
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*/
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#define IB_IOCTL_MAGIC 0x1b /* See Documentation/ioctl/ioctl-number.txt */
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/*
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* Make the ioctls occupy the last 0xf0-0xff portion of the IB range
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*/
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#define __NUM(cmd) (HFI1_CMD_##cmd + 0xe0)
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struct hfi1_cmd;
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#define HFI1_IOCTL_ASSIGN_CTXT \
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_IOWR(IB_IOCTL_MAGIC, __NUM(ASSIGN_CTXT), struct hfi1_user_info)
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#define HFI1_IOCTL_CTXT_INFO \
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_IOW(IB_IOCTL_MAGIC, __NUM(CTXT_INFO), struct hfi1_ctxt_info)
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#define HFI1_IOCTL_USER_INFO \
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_IOW(IB_IOCTL_MAGIC, __NUM(USER_INFO), struct hfi1_base_info)
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#define HFI1_IOCTL_TID_UPDATE \
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_IOWR(IB_IOCTL_MAGIC, __NUM(TID_UPDATE), struct hfi1_tid_info)
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#define HFI1_IOCTL_TID_FREE \
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_IOWR(IB_IOCTL_MAGIC, __NUM(TID_FREE), struct hfi1_tid_info)
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#define HFI1_IOCTL_CREDIT_UPD \
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_IO(IB_IOCTL_MAGIC, __NUM(CREDIT_UPD))
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#define HFI1_IOCTL_RECV_CTRL \
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_IOW(IB_IOCTL_MAGIC, __NUM(RECV_CTRL), int)
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#define HFI1_IOCTL_POLL_TYPE \
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_IOW(IB_IOCTL_MAGIC, __NUM(POLL_TYPE), int)
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#define HFI1_IOCTL_ACK_EVENT \
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_IOW(IB_IOCTL_MAGIC, __NUM(ACK_EVENT), unsigned long)
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#define HFI1_IOCTL_SET_PKEY \
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_IOW(IB_IOCTL_MAGIC, __NUM(SET_PKEY), __u16)
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#define HFI1_IOCTL_CTXT_RESET \
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_IO(IB_IOCTL_MAGIC, __NUM(CTXT_RESET))
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#define HFI1_IOCTL_TID_INVAL_READ \
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_IOWR(IB_IOCTL_MAGIC, __NUM(TID_INVAL_READ), struct hfi1_tid_info)
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#define HFI1_IOCTL_GET_VERS \
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_IOR(IB_IOCTL_MAGIC, __NUM(GET_VERS), int)
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#define _HFI1_EVENT_FROZEN_BIT 0
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#define _HFI1_EVENT_LINKDOWN_BIT 1
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#define _HFI1_EVENT_LID_CHANGE_BIT 2
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#define _HFI1_EVENT_LMC_CHANGE_BIT 3
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#define _HFI1_EVENT_SL2VL_CHANGE_BIT 4
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#define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5
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#define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MMU_NOTIFY_BIT
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#define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT)
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#define HFI1_EVENT_LINKDOWN (1UL << _HFI1_EVENT_LINKDOWN_BIT)
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#define HFI1_EVENT_LID_CHANGE (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
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#define HFI1_EVENT_LMC_CHANGE (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
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#define HFI1_EVENT_SL2VL_CHANGE (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
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#define HFI1_EVENT_TID_MMU_NOTIFY (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT)
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/*
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* These are the status bits readable (in ASCII form, 64bit value)
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* from the "status" sysfs file. For binary compatibility, values
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* must remain as is; removed states can be reused for different
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* purposes.
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*/
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#define HFI1_STATUS_INITTED 0x1 /* basic initialization done */
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/* Chip has been found and initialized */
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#define HFI1_STATUS_CHIP_PRESENT 0x20
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/* IB link is at ACTIVE, usable for data traffic */
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#define HFI1_STATUS_IB_READY 0x40
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/* link is configured, LID, MTU, etc. have been set */
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#define HFI1_STATUS_IB_CONF 0x80
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/* A Fatal hardware error has occurred. */
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#define HFI1_STATUS_HWERROR 0x200
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/*
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* Number of supported shared contexts.
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* This is the maximum number of software contexts that can share
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* a hardware send/receive context.
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*/
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#define HFI1_MAX_SHARED_CTXTS 8
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/*
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* Poll types
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*/
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#define HFI1_POLL_TYPE_ANYRCV 0x0
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#define HFI1_POLL_TYPE_URGENT 0x1
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/*
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* This structure is passed to the driver to tell it where
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* user code buffers are, sizes, etc. The offsets and sizes of the
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* fields must remain unchanged, for binary compatibility. It can
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* be extended, if userversion is changed so user code can tell, if needed
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*/
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struct hfi1_user_info {
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/*
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* version of user software, to detect compatibility issues.
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* Should be set to HFI1_USER_SWVERSION.
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*/
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__u32 userversion;
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__u32 pad;
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/*
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* If two or more processes wish to share a context, each process
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* must set the subcontext_cnt and subcontext_id to the same
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* values. The only restriction on the subcontext_id is that
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* it be unique for a given node.
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*/
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__u16 subctxt_cnt;
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__u16 subctxt_id;
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/* 128bit UUID passed in by PSM. */
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__u8 uuid[16];
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};
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struct hfi1_ctxt_info {
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__u64 runtime_flags; /* chip/drv runtime flags (HFI1_CAP_*) */
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__u32 rcvegr_size; /* size of each eager buffer */
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__u16 num_active; /* number of active units */
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__u16 unit; /* unit (chip) assigned to caller */
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__u16 ctxt; /* ctxt on unit assigned to caller */
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__u16 subctxt; /* subctxt on unit assigned to caller */
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__u16 rcvtids; /* number of Rcv TIDs for this context */
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__u16 credits; /* number of PIO credits for this context */
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__u16 numa_node; /* NUMA node of the assigned device */
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__u16 rec_cpu; /* cpu # for affinity (0xffff if none) */
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__u16 send_ctxt; /* send context in use by this user context */
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__u16 egrtids; /* number of RcvArray entries for Eager Rcvs */
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__u16 rcvhdrq_cnt; /* number of RcvHdrQ entries */
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__u16 rcvhdrq_entsize; /* size (in bytes) for each RcvHdrQ entry */
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__u16 sdma_ring_size; /* number of entries in SDMA request ring */
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};
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struct hfi1_tid_info {
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/* virtual address of first page in transfer */
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__u64 vaddr;
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/* pointer to tid array. this array is big enough */
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__u64 tidlist;
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/* number of tids programmed by this request */
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__u32 tidcnt;
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/* length of transfer buffer programmed by this request */
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__u32 length;
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};
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enum hfi1_sdma_comp_state {
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FREE = 0,
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QUEUED,
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COMPLETE,
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ERROR
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};
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/*
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* SDMA completion ring entry
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*/
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struct hfi1_sdma_comp_entry {
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__u32 status;
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__u32 errcode;
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};
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/*
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* Device status and notifications from driver to user-space.
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*/
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struct hfi1_status {
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__u64 dev; /* device/hw status bits */
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__u64 port; /* port state and status bits */
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char freezemsg[0];
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};
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/*
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* This structure is returned by the driver immediately after
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* open to get implementation-specific info, and info specific to this
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* instance.
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*
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* This struct must have explicit pad fields where type sizes
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* may result in different alignments between 32 and 64 bit
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* programs, since the 64 bit * bit kernel requires the user code
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* to have matching offsets
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*/
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struct hfi1_base_info {
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/* version of hardware, for feature checking. */
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__u32 hw_version;
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/* version of software, for feature checking. */
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__u32 sw_version;
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/* Job key */
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__u16 jkey;
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__u16 padding1;
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/*
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* The special QP (queue pair) value that identifies PSM
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* protocol packet from standard IB packets.
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*/
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__u32 bthqp;
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/* PIO credit return address, */
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__u64 sc_credits_addr;
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/*
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* Base address of write-only pio buffers for this process.
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* Each buffer has sendpio_credits*64 bytes.
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*/
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__u64 pio_bufbase_sop;
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/*
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* Base address of write-only pio buffers for this process.
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* Each buffer has sendpio_credits*64 bytes.
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*/
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__u64 pio_bufbase;
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/* address where receive buffer queue is mapped into */
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__u64 rcvhdr_bufbase;
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/* base address of Eager receive buffers. */
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__u64 rcvegr_bufbase;
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/* base address of SDMA completion ring */
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__u64 sdma_comp_bufbase;
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/*
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* User register base for init code, not to be used directly by
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* protocol or applications. Always maps real chip register space.
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* the register addresses are:
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* ur_rcvhdrhead, ur_rcvhdrtail, ur_rcvegrhead, ur_rcvegrtail,
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* ur_rcvtidflow
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*/
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__u64 user_regbase;
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/* notification events */
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__u64 events_bufbase;
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/* status page */
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__u64 status_bufbase;
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/* rcvhdrtail update */
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__u64 rcvhdrtail_base;
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/*
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* shared memory pages for subctxts if ctxt is shared; these cover
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* all the processes in the group sharing a single context.
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* all have enough space for the num_subcontexts value on this job.
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*/
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__u64 subctxt_uregbase;
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__u64 subctxt_rcvegrbuf;
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__u64 subctxt_rcvhdrbuf;
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};
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enum sdma_req_opcode {
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EXPECTED = 0,
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EAGER
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};
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#define HFI1_SDMA_REQ_VERSION_MASK 0xF
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#define HFI1_SDMA_REQ_VERSION_SHIFT 0x0
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#define HFI1_SDMA_REQ_OPCODE_MASK 0xF
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#define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4
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#define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF
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#define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8
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struct sdma_req_info {
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/*
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* bits 0-3 - version (currently unused)
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* bits 4-7 - opcode (enum sdma_req_opcode)
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* bits 8-15 - io vector count
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*/
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__u16 ctrl;
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/*
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* Number of fragments contained in this request.
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* User-space has already computed how many
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* fragment-sized packet the user buffer will be
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* split into.
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*/
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__u16 npkts;
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/*
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* Size of each fragment the user buffer will be
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* split into.
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*/
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__u16 fragsize;
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/*
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* Index of the slot in the SDMA completion ring
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* this request should be using. User-space is
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* in charge of managing its own ring.
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*/
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__u16 comp_idx;
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} __packed;
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/*
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* SW KDETH header.
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* swdata is SW defined portion.
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*/
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struct hfi1_kdeth_header {
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__le32 ver_tid_offset;
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__le16 jkey;
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__le16 hcrc;
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__le32 swdata[7];
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} __packed;
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/*
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* Structure describing the headers that User space uses. The
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* structure above is a subset of this one.
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*/
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struct hfi1_pkt_header {
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__le16 pbc[4];
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__be16 lrh[4];
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__be32 bth[3];
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struct hfi1_kdeth_header kdeth;
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} __packed;
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/*
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* The list of usermode accessible registers.
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*/
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enum hfi1_ureg {
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/* (RO) DMA RcvHdr to be used next. */
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ur_rcvhdrtail = 0,
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/* (RW) RcvHdr entry to be processed next by host. */
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ur_rcvhdrhead = 1,
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/* (RO) Index of next Eager index to use. */
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ur_rcvegrindextail = 2,
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/* (RW) Eager TID to be processed next */
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ur_rcvegrindexhead = 3,
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/* (RO) Receive Eager Offset Tail */
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ur_rcvegroffsettail = 4,
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/* For internal use only; max register number. */
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ur_maxreg,
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/* (RW) Receive TID flow table */
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ur_rcvtidflowtable = 256
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};
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#endif /* _LINIUX__HFI1_USER_H */
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