David Abdurachmanov 7ede12b01b riscv: dts: fu740: fix cache-controller interrupts ... The order of interrupt numbers is incorrect. The order for FU740 is: DirError, DataError, DataFail, DirFail From SiFive FU740-C000 Manual: 19 - L2 Cache DirError 20 - L2 Cache DirFail 21 - L2 Cache DataError 22 - L2 Cache DataFail Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2021-06-19 00:11:53 -07:00
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dts	riscv: dts: fu740: fix cache-controller interrupts	2021-06-19 00:11:53 -07:00
.gitignore	riscv: Ignore Image.* and loader.bin	2020-11-09 11:54:46 -08:00
Makefile	RISC-V: enable XIP	2021-04-26 08:31:28 -07:00
install.sh	RISC-V: Build flat and compressed kernel images	2018-11-20 05:19:09 -08:00
loader.S	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00
loader.lds.S	riscv: Move kernel mapping outside of linear mapping	2021-04-26 08:25:04 -07:00