linux/arch/x86/events/intel
Kan Liang 2dc0572f2c perf/x86/intel: Fix unchecked MSR access error caused by VLBR_EVENT
On a Haswell machine, the perf_fuzzer managed to trigger this message:

[117248.075892] unchecked MSR access error: WRMSR to 0x3f1 (tried to
write 0x0400000000000000) at rIP: 0xffffffff8106e4f4
(native_write_msr+0x4/0x20)
[117248.089957] Call Trace:
[117248.092685]  intel_pmu_pebs_enable_all+0x31/0x40
[117248.097737]  intel_pmu_enable_all+0xa/0x10
[117248.102210]  __perf_event_task_sched_in+0x2df/0x2f0
[117248.107511]  finish_task_switch.isra.0+0x15f/0x280
[117248.112765]  schedule_tail+0xc/0x40
[117248.116562]  ret_from_fork+0x8/0x30

A fake event called VLBR_EVENT may use the bit 58 of the PEBS_ENABLE, if
the precise_ip is set. The bit 58 is reserved by the HW. Accessing the
bit causes the unchecked MSR access error.

The fake event doesn't support PEBS. The case should be rejected.

Fixes: 097e4311cd ("perf/x86: Add constraint to create guest LBR event without hw counter")
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/1615555298-140216-2-git-send-email-kan.liang@linux.intel.com
2021-03-16 21:44:39 +01:00
..
Makefile perf/x86/rapl: Move RAPL support to common x86 code 2020-05-28 07:58:55 +02:00
bts.c perf/x86: Replace zero-length array with flexible-array 2020-05-19 20:34:16 +02:00
core.c perf/x86/intel: Fix unchecked MSR access error caused by VLBR_EVENT 2021-03-16 21:44:39 +01:00
cstate.c Merge remote-tracking branch 'origin/master' into perf/core 2020-11-26 13:16:55 +01:00
ds.c perf/x86/intel: Fix a crash caused by zero PEBS status 2021-03-16 21:44:39 +01:00
knc.c License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
lbr.c Perf updates: 2020-12-14 17:34:12 -08:00
p4.c perf_event: Add support for LSM and SELinux checks 2019-10-17 21:31:55 +02:00
p6.c x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping 2018-02-15 01:15:52 +01:00
pt.c perf/x86/intel/pt: Drop pointless NULL assignment. 2020-04-30 20:14:36 +02:00
pt.h perf/x86/intel/pt: Prevent redundant WRMSRs 2019-11-13 11:06:18 +01:00
uncore.c perf/x86/intel/uncore: Store the logical die id instead of the physical die id. 2021-01-14 11:20:13 +01:00
uncore.h perf/x86/intel/uncore: Store the logical die id instead of the physical die id. 2021-01-14 11:20:13 +01:00
uncore_nhmex.c perf/x86/intel/uncore: Correct fixed counter index check for NHM 2018-05-31 12:36:28 +02:00
uncore_snb.c perf/x86/intel/uncore: Store the logical die id instead of the physical die id. 2021-01-14 11:20:13 +01:00
uncore_snbep.c perf/x86/intel/uncore: With > 8 nodes, get pci bus die id from NUMA info 2021-01-14 11:20:14 +01:00