mirror of https://gitee.com/openkylin/linux.git
654 lines
19 KiB
C
654 lines
19 KiB
C
/*
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* Regulator Driver for Freescale MC13892 PMIC
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*
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* Copyright 2010 Yong Shen <yong.shen@linaro.org>
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*
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* Based on draft driver from Arnaud Patard <arnaud.patard@rtp-net.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/mfd/mc13892.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/driver.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include "mc13xxx.h"
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#define MC13892_REVISION 7
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#define MC13892_POWERCTL0 13
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#define MC13892_POWERCTL0_USEROFFSPI 3
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#define MC13892_POWERCTL0_VCOINCELLVSEL 20
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#define MC13892_POWERCTL0_VCOINCELLVSEL_M (7<<20)
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#define MC13892_POWERCTL0_VCOINCELLEN (1<<23)
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#define MC13892_SWITCHERS0_SWxHI (1<<23)
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#define MC13892_SWITCHERS0 24
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#define MC13892_SWITCHERS0_SW1VSEL 0
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#define MC13892_SWITCHERS0_SW1VSEL_M (0x1f<<0)
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#define MC13892_SWITCHERS0_SW1HI (1<<23)
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#define MC13892_SWITCHERS0_SW1EN 0
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#define MC13892_SWITCHERS1 25
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#define MC13892_SWITCHERS1_SW2VSEL 0
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#define MC13892_SWITCHERS1_SW2VSEL_M (0x1f<<0)
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#define MC13892_SWITCHERS1_SW2HI (1<<23)
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#define MC13892_SWITCHERS1_SW2EN 0
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#define MC13892_SWITCHERS2 26
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#define MC13892_SWITCHERS2_SW3VSEL 0
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#define MC13892_SWITCHERS2_SW3VSEL_M (0x1f<<0)
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#define MC13892_SWITCHERS2_SW3HI (1<<23)
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#define MC13892_SWITCHERS2_SW3EN 0
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#define MC13892_SWITCHERS3 27
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#define MC13892_SWITCHERS3_SW4VSEL 0
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#define MC13892_SWITCHERS3_SW4VSEL_M (0x1f<<0)
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#define MC13892_SWITCHERS3_SW4HI (1<<23)
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#define MC13892_SWITCHERS3_SW4EN 0
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#define MC13892_SWITCHERS4 28
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#define MC13892_SWITCHERS4_SW1MODE 0
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#define MC13892_SWITCHERS4_SW1MODE_AUTO (8<<0)
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#define MC13892_SWITCHERS4_SW1MODE_M (0xf<<0)
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#define MC13892_SWITCHERS4_SW2MODE 10
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#define MC13892_SWITCHERS4_SW2MODE_AUTO (8<<10)
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#define MC13892_SWITCHERS4_SW2MODE_M (0xf<<10)
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#define MC13892_SWITCHERS5 29
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#define MC13892_SWITCHERS5_SW3MODE 0
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#define MC13892_SWITCHERS5_SW3MODE_AUTO (8<<0)
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#define MC13892_SWITCHERS5_SW3MODE_M (0xf<<0)
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#define MC13892_SWITCHERS5_SW4MODE 8
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#define MC13892_SWITCHERS5_SW4MODE_AUTO (8<<8)
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#define MC13892_SWITCHERS5_SW4MODE_M (0xf<<8)
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#define MC13892_SWITCHERS5_SWBSTEN (1<<20)
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#define MC13892_REGULATORSETTING0 30
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#define MC13892_REGULATORSETTING0_VGEN1VSEL 0
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#define MC13892_REGULATORSETTING0_VDIGVSEL 4
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#define MC13892_REGULATORSETTING0_VGEN2VSEL 6
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#define MC13892_REGULATORSETTING0_VPLLVSEL 9
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#define MC13892_REGULATORSETTING0_VUSB2VSEL 11
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#define MC13892_REGULATORSETTING0_VGEN3VSEL 14
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#define MC13892_REGULATORSETTING0_VCAMVSEL 16
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#define MC13892_REGULATORSETTING0_VGEN1VSEL_M (3<<0)
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#define MC13892_REGULATORSETTING0_VDIGVSEL_M (3<<4)
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#define MC13892_REGULATORSETTING0_VGEN2VSEL_M (7<<6)
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#define MC13892_REGULATORSETTING0_VPLLVSEL_M (3<<9)
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#define MC13892_REGULATORSETTING0_VUSB2VSEL_M (3<<11)
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#define MC13892_REGULATORSETTING0_VGEN3VSEL_M (1<<14)
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#define MC13892_REGULATORSETTING0_VCAMVSEL_M (3<<16)
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#define MC13892_REGULATORSETTING1 31
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#define MC13892_REGULATORSETTING1_VVIDEOVSEL 2
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#define MC13892_REGULATORSETTING1_VAUDIOVSEL 4
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#define MC13892_REGULATORSETTING1_VSDVSEL 6
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#define MC13892_REGULATORSETTING1_VVIDEOVSEL_M (3<<2)
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#define MC13892_REGULATORSETTING1_VAUDIOVSEL_M (3<<4)
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#define MC13892_REGULATORSETTING1_VSDVSEL_M (7<<6)
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#define MC13892_REGULATORMODE0 32
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#define MC13892_REGULATORMODE0_VGEN1EN (1<<0)
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#define MC13892_REGULATORMODE0_VGEN1STDBY (1<<1)
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#define MC13892_REGULATORMODE0_VGEN1MODE (1<<2)
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#define MC13892_REGULATORMODE0_VIOHIEN (1<<3)
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#define MC13892_REGULATORMODE0_VIOHISTDBY (1<<4)
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#define MC13892_REGULATORMODE0_VIOHIMODE (1<<5)
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#define MC13892_REGULATORMODE0_VDIGEN (1<<9)
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#define MC13892_REGULATORMODE0_VDIGSTDBY (1<<10)
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#define MC13892_REGULATORMODE0_VDIGMODE (1<<11)
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#define MC13892_REGULATORMODE0_VGEN2EN (1<<12)
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#define MC13892_REGULATORMODE0_VGEN2STDBY (1<<13)
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#define MC13892_REGULATORMODE0_VGEN2MODE (1<<14)
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#define MC13892_REGULATORMODE0_VPLLEN (1<<15)
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#define MC13892_REGULATORMODE0_VPLLSTDBY (1<<16)
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#define MC13892_REGULATORMODE0_VPLLMODE (1<<17)
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#define MC13892_REGULATORMODE0_VUSB2EN (1<<18)
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#define MC13892_REGULATORMODE0_VUSB2STDBY (1<<19)
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#define MC13892_REGULATORMODE0_VUSB2MODE (1<<20)
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#define MC13892_REGULATORMODE1 33
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#define MC13892_REGULATORMODE1_VGEN3EN (1<<0)
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#define MC13892_REGULATORMODE1_VGEN3STDBY (1<<1)
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#define MC13892_REGULATORMODE1_VGEN3MODE (1<<2)
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#define MC13892_REGULATORMODE1_VCAMEN (1<<6)
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#define MC13892_REGULATORMODE1_VCAMSTDBY (1<<7)
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#define MC13892_REGULATORMODE1_VCAMMODE (1<<8)
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#define MC13892_REGULATORMODE1_VCAMCONFIGEN (1<<9)
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#define MC13892_REGULATORMODE1_VVIDEOEN (1<<12)
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#define MC13892_REGULATORMODE1_VVIDEOSTDBY (1<<13)
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#define MC13892_REGULATORMODE1_VVIDEOMODE (1<<14)
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#define MC13892_REGULATORMODE1_VAUDIOEN (1<<15)
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#define MC13892_REGULATORMODE1_VAUDIOSTDBY (1<<16)
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#define MC13892_REGULATORMODE1_VAUDIOMODE (1<<17)
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#define MC13892_REGULATORMODE1_VSDEN (1<<18)
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#define MC13892_REGULATORMODE1_VSDSTDBY (1<<19)
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#define MC13892_REGULATORMODE1_VSDMODE (1<<20)
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#define MC13892_POWERMISC 34
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#define MC13892_POWERMISC_GPO1EN (1<<6)
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#define MC13892_POWERMISC_GPO2EN (1<<8)
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#define MC13892_POWERMISC_GPO3EN (1<<10)
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#define MC13892_POWERMISC_GPO4EN (1<<12)
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#define MC13892_POWERMISC_PWGT1SPIEN (1<<15)
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#define MC13892_POWERMISC_PWGT2SPIEN (1<<16)
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#define MC13892_POWERMISC_GPO4ADINEN (1<<21)
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#define MC13892_POWERMISC_PWGTSPI_M (3 << 15)
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#define MC13892_USB1 50
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#define MC13892_USB1_VUSBEN (1<<3)
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static const unsigned int mc13892_vcoincell[] = {
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2500000, 2700000, 2800000, 2900000, 3000000, 3100000,
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3200000, 3300000,
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};
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static const unsigned int mc13892_sw1[] = {
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600000, 625000, 650000, 675000, 700000, 725000,
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750000, 775000, 800000, 825000, 850000, 875000,
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900000, 925000, 950000, 975000, 1000000, 1025000,
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1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
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1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
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1350000, 1375000
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};
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static const unsigned int mc13892_sw[] = {
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600000, 625000, 650000, 675000, 700000, 725000,
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750000, 775000, 800000, 825000, 850000, 875000,
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900000, 925000, 950000, 975000, 1000000, 1025000,
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1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
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1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
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1350000, 1375000, 1400000, 1425000, 1450000, 1475000,
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1500000, 1525000, 1550000, 1575000, 1600000, 1625000,
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1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
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1800000, 1825000, 1850000, 1875000
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};
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static const unsigned int mc13892_swbst[] = {
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5000000,
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};
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static const unsigned int mc13892_viohi[] = {
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2775000,
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};
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static const unsigned int mc13892_vpll[] = {
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1050000, 1250000, 1650000, 1800000,
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};
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static const unsigned int mc13892_vdig[] = {
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1050000, 1250000, 1650000, 1800000,
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};
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static const unsigned int mc13892_vsd[] = {
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1800000, 2000000, 2600000, 2700000,
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2800000, 2900000, 3000000, 3150000,
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};
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static const unsigned int mc13892_vusb2[] = {
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2400000, 2600000, 2700000, 2775000,
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};
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static const unsigned int mc13892_vvideo[] = {
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2700000, 2775000, 2500000, 2600000,
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};
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static const unsigned int mc13892_vaudio[] = {
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2300000, 2500000, 2775000, 3000000,
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};
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static const unsigned int mc13892_vcam[] = {
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2500000, 2600000, 2750000, 3000000,
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};
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static const unsigned int mc13892_vgen1[] = {
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1200000, 1500000, 2775000, 3150000,
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};
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static const unsigned int mc13892_vgen2[] = {
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1200000, 1500000, 1600000, 1800000,
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2700000, 2800000, 3000000, 3150000,
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};
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static const unsigned int mc13892_vgen3[] = {
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1800000, 2900000,
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};
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static const unsigned int mc13892_vusb[] = {
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3300000,
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};
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static const unsigned int mc13892_gpo[] = {
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2750000,
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};
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static const unsigned int mc13892_pwgtdrv[] = {
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5000000,
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};
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static struct regulator_ops mc13892_gpo_regulator_ops;
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/* sw regulators need special care due to the "hi bit" */
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static struct regulator_ops mc13892_sw_regulator_ops;
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#define MC13892_FIXED_DEFINE(name, reg, voltages) \
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MC13xxx_FIXED_DEFINE(MC13892_, name, reg, voltages, \
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mc13xxx_fixed_regulator_ops)
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#define MC13892_GPO_DEFINE(name, reg, voltages) \
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MC13xxx_GPO_DEFINE(MC13892_, name, reg, voltages, \
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mc13892_gpo_regulator_ops)
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#define MC13892_SW_DEFINE(name, reg, vsel_reg, voltages) \
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MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \
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mc13892_sw_regulator_ops)
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#define MC13892_DEFINE_REGU(name, reg, vsel_reg, voltages) \
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MC13xxx_DEFINE(MC13892_, name, reg, vsel_reg, voltages, \
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mc13xxx_regulator_ops)
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static struct mc13xxx_regulator mc13892_regulators[] = {
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MC13892_DEFINE_REGU(VCOINCELL, POWERCTL0, POWERCTL0, mc13892_vcoincell),
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MC13892_SW_DEFINE(SW1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
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MC13892_SW_DEFINE(SW2, SWITCHERS1, SWITCHERS1, mc13892_sw),
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MC13892_SW_DEFINE(SW3, SWITCHERS2, SWITCHERS2, mc13892_sw),
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MC13892_SW_DEFINE(SW4, SWITCHERS3, SWITCHERS3, mc13892_sw),
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MC13892_FIXED_DEFINE(SWBST, SWITCHERS5, mc13892_swbst),
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MC13892_FIXED_DEFINE(VIOHI, REGULATORMODE0, mc13892_viohi),
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MC13892_DEFINE_REGU(VPLL, REGULATORMODE0, REGULATORSETTING0, \
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mc13892_vpll),
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MC13892_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \
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mc13892_vdig),
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MC13892_DEFINE_REGU(VSD, REGULATORMODE1, REGULATORSETTING1, \
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mc13892_vsd),
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MC13892_DEFINE_REGU(VUSB2, REGULATORMODE0, REGULATORSETTING0, \
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mc13892_vusb2),
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MC13892_DEFINE_REGU(VVIDEO, REGULATORMODE1, REGULATORSETTING1, \
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mc13892_vvideo),
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MC13892_DEFINE_REGU(VAUDIO, REGULATORMODE1, REGULATORSETTING1, \
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mc13892_vaudio),
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MC13892_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \
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mc13892_vcam),
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MC13892_DEFINE_REGU(VGEN1, REGULATORMODE0, REGULATORSETTING0, \
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mc13892_vgen1),
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MC13892_DEFINE_REGU(VGEN2, REGULATORMODE0, REGULATORSETTING0, \
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mc13892_vgen2),
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MC13892_DEFINE_REGU(VGEN3, REGULATORMODE1, REGULATORSETTING0, \
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mc13892_vgen3),
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MC13892_FIXED_DEFINE(VUSB, USB1, mc13892_vusb),
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MC13892_GPO_DEFINE(GPO1, POWERMISC, mc13892_gpo),
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MC13892_GPO_DEFINE(GPO2, POWERMISC, mc13892_gpo),
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MC13892_GPO_DEFINE(GPO3, POWERMISC, mc13892_gpo),
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MC13892_GPO_DEFINE(GPO4, POWERMISC, mc13892_gpo),
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MC13892_GPO_DEFINE(PWGT1SPI, POWERMISC, mc13892_pwgtdrv),
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MC13892_GPO_DEFINE(PWGT2SPI, POWERMISC, mc13892_pwgtdrv),
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};
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static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
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u32 val)
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{
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struct mc13xxx *mc13892 = priv->mc13xxx;
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int ret;
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u32 valread;
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BUG_ON(val & ~mask);
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ret = mc13xxx_reg_read(mc13892, MC13892_POWERMISC, &valread);
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if (ret)
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return ret;
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/* Update the stored state for Power Gates. */
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priv->powermisc_pwgt_state =
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(priv->powermisc_pwgt_state & ~mask) | val;
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priv->powermisc_pwgt_state &= MC13892_POWERMISC_PWGTSPI_M;
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/* Construct the new register value */
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valread = (valread & ~mask) | val;
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/* Overwrite the PWGTxEN with the stored version */
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valread = (valread & ~MC13892_POWERMISC_PWGTSPI_M) |
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priv->powermisc_pwgt_state;
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return mc13xxx_reg_write(mc13892, MC13892_POWERMISC, valread);
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}
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static int mc13892_gpo_regulator_enable(struct regulator_dev *rdev)
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{
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struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
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int id = rdev_get_id(rdev);
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int ret;
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u32 en_val = mc13892_regulators[id].enable_bit;
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u32 mask = mc13892_regulators[id].enable_bit;
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dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
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/* Power Gate enable value is 0 */
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if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
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en_val = 0;
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if (id == MC13892_GPO4)
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mask |= MC13892_POWERMISC_GPO4ADINEN;
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mc13xxx_lock(priv->mc13xxx);
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ret = mc13892_powermisc_rmw(priv, mask, en_val);
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mc13xxx_unlock(priv->mc13xxx);
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return ret;
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}
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static int mc13892_gpo_regulator_disable(struct regulator_dev *rdev)
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{
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struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
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int id = rdev_get_id(rdev);
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int ret;
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u32 dis_val = 0;
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dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
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/* Power Gate disable value is 1 */
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if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
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dis_val = mc13892_regulators[id].enable_bit;
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mc13xxx_lock(priv->mc13xxx);
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ret = mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit,
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dis_val);
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mc13xxx_unlock(priv->mc13xxx);
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return ret;
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}
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static int mc13892_gpo_regulator_is_enabled(struct regulator_dev *rdev)
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{
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struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
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int ret, id = rdev_get_id(rdev);
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unsigned int val;
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mc13xxx_lock(priv->mc13xxx);
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ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
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mc13xxx_unlock(priv->mc13xxx);
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if (ret)
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return ret;
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/* Power Gates state is stored in powermisc_pwgt_state
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* where the meaning of bits is negated */
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val = (val & ~MC13892_POWERMISC_PWGTSPI_M) |
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(priv->powermisc_pwgt_state ^ MC13892_POWERMISC_PWGTSPI_M);
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return (val & mc13892_regulators[id].enable_bit) != 0;
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}
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static struct regulator_ops mc13892_gpo_regulator_ops = {
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.enable = mc13892_gpo_regulator_enable,
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.disable = mc13892_gpo_regulator_disable,
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.is_enabled = mc13892_gpo_regulator_is_enabled,
|
|
.list_voltage = regulator_list_voltage_table,
|
|
.set_voltage = mc13xxx_fixed_regulator_set_voltage,
|
|
.get_voltage = mc13xxx_fixed_regulator_get_voltage,
|
|
};
|
|
|
|
static int mc13892_sw_regulator_get_voltage(struct regulator_dev *rdev)
|
|
{
|
|
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
|
|
int ret, id = rdev_get_id(rdev);
|
|
unsigned int val, hi;
|
|
|
|
dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
|
|
|
|
mc13xxx_lock(priv->mc13xxx);
|
|
ret = mc13xxx_reg_read(priv->mc13xxx,
|
|
mc13892_regulators[id].vsel_reg, &val);
|
|
mc13xxx_unlock(priv->mc13xxx);
|
|
if (ret)
|
|
return ret;
|
|
|
|
hi = val & MC13892_SWITCHERS0_SWxHI;
|
|
val = (val & mc13892_regulators[id].vsel_mask)
|
|
>> mc13892_regulators[id].vsel_shift;
|
|
|
|
dev_dbg(rdev_get_dev(rdev), "%s id: %d val: %d\n", __func__, id, val);
|
|
|
|
if (hi)
|
|
val = (25000 * val) + 1100000;
|
|
else
|
|
val = (25000 * val) + 600000;
|
|
|
|
return val;
|
|
}
|
|
|
|
static int mc13892_sw_regulator_set_voltage_sel(struct regulator_dev *rdev,
|
|
unsigned selector)
|
|
{
|
|
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
|
|
int hi, value, mask, id = rdev_get_id(rdev);
|
|
u32 valread;
|
|
int ret;
|
|
|
|
value = rdev->desc->volt_table[selector];
|
|
|
|
mc13xxx_lock(priv->mc13xxx);
|
|
ret = mc13xxx_reg_read(priv->mc13xxx,
|
|
mc13892_regulators[id].vsel_reg, &valread);
|
|
if (ret)
|
|
goto err;
|
|
|
|
if (value > 1375000)
|
|
hi = 1;
|
|
else if (value < 1100000)
|
|
hi = 0;
|
|
else
|
|
hi = valread & MC13892_SWITCHERS0_SWxHI;
|
|
|
|
if (hi) {
|
|
value = (value - 1100000) / 25000;
|
|
value |= MC13892_SWITCHERS0_SWxHI;
|
|
} else
|
|
value = (value - 600000) / 25000;
|
|
|
|
mask = mc13892_regulators[id].vsel_mask | MC13892_SWITCHERS0_SWxHI;
|
|
valread = (valread & ~mask) |
|
|
(value << mc13892_regulators[id].vsel_shift);
|
|
ret = mc13xxx_reg_write(priv->mc13xxx, mc13892_regulators[id].vsel_reg,
|
|
valread);
|
|
err:
|
|
mc13xxx_unlock(priv->mc13xxx);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct regulator_ops mc13892_sw_regulator_ops = {
|
|
.list_voltage = regulator_list_voltage_table,
|
|
.set_voltage_sel = mc13892_sw_regulator_set_voltage_sel,
|
|
.get_voltage = mc13892_sw_regulator_get_voltage,
|
|
};
|
|
|
|
static int mc13892_vcam_set_mode(struct regulator_dev *rdev, unsigned int mode)
|
|
{
|
|
unsigned int en_val = 0;
|
|
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
|
|
int ret, id = rdev_get_id(rdev);
|
|
|
|
if (mode == REGULATOR_MODE_FAST)
|
|
en_val = MC13892_REGULATORMODE1_VCAMCONFIGEN;
|
|
|
|
mc13xxx_lock(priv->mc13xxx);
|
|
ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg,
|
|
MC13892_REGULATORMODE1_VCAMCONFIGEN, en_val);
|
|
mc13xxx_unlock(priv->mc13xxx);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static unsigned int mc13892_vcam_get_mode(struct regulator_dev *rdev)
|
|
{
|
|
struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
|
|
int ret, id = rdev_get_id(rdev);
|
|
unsigned int val;
|
|
|
|
mc13xxx_lock(priv->mc13xxx);
|
|
ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
|
|
mc13xxx_unlock(priv->mc13xxx);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN)
|
|
return REGULATOR_MODE_FAST;
|
|
|
|
return REGULATOR_MODE_NORMAL;
|
|
}
|
|
|
|
|
|
static int __devinit mc13892_regulator_probe(struct platform_device *pdev)
|
|
{
|
|
struct mc13xxx_regulator_priv *priv;
|
|
struct mc13xxx *mc13892 = dev_get_drvdata(pdev->dev.parent);
|
|
struct mc13xxx_regulator_platform_data *pdata =
|
|
dev_get_platdata(&pdev->dev);
|
|
struct mc13xxx_regulator_init_data *mc13xxx_data;
|
|
struct regulator_config config = { };
|
|
int i, ret;
|
|
int num_regulators = 0;
|
|
u32 val;
|
|
|
|
num_regulators = mc13xxx_get_num_regulators_dt(pdev);
|
|
if (num_regulators <= 0 && pdata)
|
|
num_regulators = pdata->num_regulators;
|
|
if (num_regulators <= 0)
|
|
return -EINVAL;
|
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv) +
|
|
num_regulators * sizeof(priv->regulators[0]),
|
|
GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->num_regulators = num_regulators;
|
|
priv->mc13xxx_regulators = mc13892_regulators;
|
|
priv->mc13xxx = mc13892;
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
mc13xxx_lock(mc13892);
|
|
ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val);
|
|
if (ret)
|
|
goto err_unlock;
|
|
|
|
/* enable switch auto mode */
|
|
if ((val & 0x0000FFFF) == 0x45d0) {
|
|
ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS4,
|
|
MC13892_SWITCHERS4_SW1MODE_M |
|
|
MC13892_SWITCHERS4_SW2MODE_M,
|
|
MC13892_SWITCHERS4_SW1MODE_AUTO |
|
|
MC13892_SWITCHERS4_SW2MODE_AUTO);
|
|
if (ret)
|
|
goto err_unlock;
|
|
|
|
ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS5,
|
|
MC13892_SWITCHERS5_SW3MODE_M |
|
|
MC13892_SWITCHERS5_SW4MODE_M,
|
|
MC13892_SWITCHERS5_SW3MODE_AUTO |
|
|
MC13892_SWITCHERS5_SW4MODE_AUTO);
|
|
if (ret)
|
|
goto err_unlock;
|
|
}
|
|
mc13xxx_unlock(mc13892);
|
|
|
|
mc13892_regulators[MC13892_VCAM].desc.ops->set_mode
|
|
= mc13892_vcam_set_mode;
|
|
mc13892_regulators[MC13892_VCAM].desc.ops->get_mode
|
|
= mc13892_vcam_get_mode;
|
|
|
|
mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13892_regulators,
|
|
ARRAY_SIZE(mc13892_regulators));
|
|
for (i = 0; i < num_regulators; i++) {
|
|
struct regulator_init_data *init_data;
|
|
struct regulator_desc *desc;
|
|
struct device_node *node = NULL;
|
|
int id;
|
|
|
|
if (mc13xxx_data) {
|
|
id = mc13xxx_data[i].id;
|
|
init_data = mc13xxx_data[i].init_data;
|
|
node = mc13xxx_data[i].node;
|
|
} else {
|
|
id = pdata->regulators[i].id;
|
|
init_data = pdata->regulators[i].init_data;
|
|
}
|
|
desc = &mc13892_regulators[id].desc;
|
|
|
|
config.dev = &pdev->dev;
|
|
config.init_data = init_data;
|
|
config.driver_data = priv;
|
|
config.of_node = node;
|
|
|
|
priv->regulators[i] = regulator_register(desc, &config);
|
|
if (IS_ERR(priv->regulators[i])) {
|
|
dev_err(&pdev->dev, "failed to register regulator %s\n",
|
|
mc13892_regulators[i].desc.name);
|
|
ret = PTR_ERR(priv->regulators[i]);
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
err:
|
|
while (--i >= 0)
|
|
regulator_unregister(priv->regulators[i]);
|
|
return ret;
|
|
|
|
err_unlock:
|
|
mc13xxx_unlock(mc13892);
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit mc13892_regulator_remove(struct platform_device *pdev)
|
|
{
|
|
struct mc13xxx_regulator_priv *priv = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
for (i = 0; i < priv->num_regulators; i++)
|
|
regulator_unregister(priv->regulators[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver mc13892_regulator_driver = {
|
|
.driver = {
|
|
.name = "mc13892-regulator",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.remove = __devexit_p(mc13892_regulator_remove),
|
|
.probe = mc13892_regulator_probe,
|
|
};
|
|
|
|
static int __init mc13892_regulator_init(void)
|
|
{
|
|
return platform_driver_register(&mc13892_regulator_driver);
|
|
}
|
|
subsys_initcall(mc13892_regulator_init);
|
|
|
|
static void __exit mc13892_regulator_exit(void)
|
|
{
|
|
platform_driver_unregister(&mc13892_regulator_driver);
|
|
}
|
|
module_exit(mc13892_regulator_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Yong Shen <yong.shen@linaro.org>");
|
|
MODULE_DESCRIPTION("Regulator Driver for Freescale MC13892 PMIC");
|
|
MODULE_ALIAS("platform:mc13892-regulator");
|