mirror of https://gitee.com/openkylin/linux.git
433 lines
16 KiB
C
433 lines
16 KiB
C
#ifndef ADRENO_COMMON_XML
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#define ADRENO_COMMON_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial
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portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum adreno_pa_su_sc_draw {
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PC_DRAW_POINTS = 0,
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PC_DRAW_LINES = 1,
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PC_DRAW_TRIANGLES = 2,
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};
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enum adreno_compare_func {
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FUNC_NEVER = 0,
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FUNC_LESS = 1,
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FUNC_EQUAL = 2,
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FUNC_LEQUAL = 3,
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FUNC_GREATER = 4,
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FUNC_NOTEQUAL = 5,
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FUNC_GEQUAL = 6,
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FUNC_ALWAYS = 7,
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};
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enum adreno_stencil_op {
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STENCIL_KEEP = 0,
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STENCIL_ZERO = 1,
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STENCIL_REPLACE = 2,
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STENCIL_INCR_CLAMP = 3,
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STENCIL_DECR_CLAMP = 4,
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STENCIL_INVERT = 5,
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STENCIL_INCR_WRAP = 6,
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STENCIL_DECR_WRAP = 7,
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};
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enum adreno_rb_blend_factor {
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FACTOR_ZERO = 0,
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FACTOR_ONE = 1,
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FACTOR_SRC_COLOR = 4,
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FACTOR_ONE_MINUS_SRC_COLOR = 5,
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FACTOR_SRC_ALPHA = 6,
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FACTOR_ONE_MINUS_SRC_ALPHA = 7,
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FACTOR_DST_COLOR = 8,
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FACTOR_ONE_MINUS_DST_COLOR = 9,
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FACTOR_DST_ALPHA = 10,
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FACTOR_ONE_MINUS_DST_ALPHA = 11,
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FACTOR_CONSTANT_COLOR = 12,
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FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
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FACTOR_CONSTANT_ALPHA = 14,
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FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
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FACTOR_SRC_ALPHA_SATURATE = 16,
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};
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enum adreno_rb_blend_opcode {
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BLEND_DST_PLUS_SRC = 0,
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BLEND_SRC_MINUS_DST = 1,
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BLEND_MIN_DST_SRC = 2,
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BLEND_MAX_DST_SRC = 3,
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BLEND_DST_MINUS_SRC = 4,
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BLEND_DST_PLUS_SRC_BIAS = 5,
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};
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enum adreno_rb_surface_endian {
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ENDIAN_NONE = 0,
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ENDIAN_8IN16 = 1,
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ENDIAN_8IN32 = 2,
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ENDIAN_16IN32 = 3,
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ENDIAN_8IN64 = 4,
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ENDIAN_8IN128 = 5,
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};
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enum adreno_rb_dither_mode {
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DITHER_DISABLE = 0,
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DITHER_ALWAYS = 1,
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DITHER_IF_ALPHA_OFF = 2,
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};
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enum adreno_rb_depth_format {
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DEPTHX_16 = 0,
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DEPTHX_24_8 = 1,
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};
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enum adreno_mmu_clnt_beh {
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BEH_NEVR = 0,
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BEH_TRAN_RNG = 1,
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BEH_TRAN_FLT = 2,
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};
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#define REG_AXXX_MH_MMU_CONFIG 0x00000040
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#define AXXX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001
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#define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002
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#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030
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#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4
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static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0
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#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6
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static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300
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#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8
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static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00
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#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10
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static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000
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#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12
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static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000
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#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14
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static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000
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#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16
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static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000
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#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18
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static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000
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#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20
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static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000
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#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22
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static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
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}
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#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000
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#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24
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static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
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}
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#define REG_AXXX_MH_MMU_VA_RANGE 0x00000041
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#define REG_AXXX_MH_MMU_PT_BASE 0x00000042
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#define REG_AXXX_MH_MMU_PAGE_FAULT 0x00000043
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#define REG_AXXX_MH_MMU_TRAN_ERROR 0x00000044
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#define REG_AXXX_MH_MMU_INVALIDATE 0x00000045
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#define REG_AXXX_MH_MMU_MPU_BASE 0x00000046
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#define REG_AXXX_MH_MMU_MPU_END 0x00000047
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#define REG_AXXX_CP_RB_BASE 0x000001c0
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#define REG_AXXX_CP_RB_CNTL 0x000001c1
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#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
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#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
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static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
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{
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return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
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}
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#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
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#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
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static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
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{
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return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
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}
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#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
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#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
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static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
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{
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return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
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}
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#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
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#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
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#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
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#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
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#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
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#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
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static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
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{
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return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
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}
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#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
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#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
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static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
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{
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return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
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}
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#define REG_AXXX_CP_RB_RPTR 0x000001c4
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#define REG_AXXX_CP_RB_WPTR 0x000001c5
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#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
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#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
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#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
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#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
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static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
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{
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return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
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}
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
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static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
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{
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return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
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}
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
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#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
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static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
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{
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return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
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}
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#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
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#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
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#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
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#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
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static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
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}
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#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
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#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
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static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
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}
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#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
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#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
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static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
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}
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#define REG_AXXX_CP_STQ_AVAIL 0x000001d8
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#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
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#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
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static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
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{
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return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
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}
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#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
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#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
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#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
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static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
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{
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return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
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}
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#define REG_AXXX_SCRATCH_UMSK 0x000001dc
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#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
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#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
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static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
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{
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return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
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}
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#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
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#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
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static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
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{
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return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
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}
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#define REG_AXXX_SCRATCH_ADDR 0x000001dd
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#define REG_AXXX_CP_ME_RDADDR 0x000001ea
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#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
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#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
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#define REG_AXXX_CP_INT_CNTL 0x000001f2
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#define REG_AXXX_CP_INT_STATUS 0x000001f3
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#define REG_AXXX_CP_INT_ACK 0x000001f4
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#define REG_AXXX_CP_ME_CNTL 0x000001f6
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#define REG_AXXX_CP_ME_STATUS 0x000001f7
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#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
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#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
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#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
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#define REG_AXXX_CP_DEBUG 0x000001fc
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#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
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#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
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#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
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#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
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#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
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#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
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#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
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#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
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#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
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#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
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#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
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static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
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}
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#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
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#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
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static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
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}
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#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
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#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
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#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
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static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
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}
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#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
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#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
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static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
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}
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#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
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#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
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#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
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static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
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}
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#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
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#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
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static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
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{
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return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
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}
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#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
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#define REG_AXXX_CP_SCRATCH_REG1 0x00000579
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#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
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#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
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#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
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#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
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#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
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#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
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#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
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#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
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#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
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#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
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#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
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#endif /* ADRENO_COMMON_XML */
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