mirror of https://gitee.com/openkylin/linux.git
217 lines
6.9 KiB
C
217 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX5_H
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#define __DT_BINDINGS_CLOCK_IMX5_H
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#define IMX5_CLK_DUMMY 0
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#define IMX5_CLK_CKIL 1
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#define IMX5_CLK_OSC 2
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#define IMX5_CLK_CKIH1 3
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#define IMX5_CLK_CKIH2 4
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#define IMX5_CLK_AHB 5
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#define IMX5_CLK_IPG 6
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#define IMX5_CLK_AXI_A 7
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#define IMX5_CLK_AXI_B 8
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#define IMX5_CLK_UART_PRED 9
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#define IMX5_CLK_UART_ROOT 10
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#define IMX5_CLK_ESDHC_A_PRED 11
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#define IMX5_CLK_ESDHC_B_PRED 12
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#define IMX5_CLK_ESDHC_C_SEL 13
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#define IMX5_CLK_ESDHC_D_SEL 14
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#define IMX5_CLK_EMI_SEL 15
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#define IMX5_CLK_EMI_SLOW_PODF 16
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#define IMX5_CLK_NFC_PODF 17
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#define IMX5_CLK_ECSPI_PRED 18
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#define IMX5_CLK_ECSPI_PODF 19
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#define IMX5_CLK_USBOH3_PRED 20
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#define IMX5_CLK_USBOH3_PODF 21
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#define IMX5_CLK_USB_PHY_PRED 22
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#define IMX5_CLK_USB_PHY_PODF 23
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#define IMX5_CLK_CPU_PODF 24
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#define IMX5_CLK_DI_PRED 25
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#define IMX5_CLK_TVE_SEL 27
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#define IMX5_CLK_UART1_IPG_GATE 28
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#define IMX5_CLK_UART1_PER_GATE 29
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#define IMX5_CLK_UART2_IPG_GATE 30
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#define IMX5_CLK_UART2_PER_GATE 31
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#define IMX5_CLK_UART3_IPG_GATE 32
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#define IMX5_CLK_UART3_PER_GATE 33
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#define IMX5_CLK_I2C1_GATE 34
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#define IMX5_CLK_I2C2_GATE 35
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#define IMX5_CLK_GPT_IPG_GATE 36
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#define IMX5_CLK_PWM1_IPG_GATE 37
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#define IMX5_CLK_PWM1_HF_GATE 38
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#define IMX5_CLK_PWM2_IPG_GATE 39
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#define IMX5_CLK_PWM2_HF_GATE 40
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#define IMX5_CLK_GPT_HF_GATE 41
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#define IMX5_CLK_FEC_GATE 42
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#define IMX5_CLK_USBOH3_PER_GATE 43
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#define IMX5_CLK_ESDHC1_IPG_GATE 44
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#define IMX5_CLK_ESDHC2_IPG_GATE 45
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#define IMX5_CLK_ESDHC3_IPG_GATE 46
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#define IMX5_CLK_ESDHC4_IPG_GATE 47
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#define IMX5_CLK_SSI1_IPG_GATE 48
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#define IMX5_CLK_SSI2_IPG_GATE 49
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#define IMX5_CLK_SSI3_IPG_GATE 50
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#define IMX5_CLK_ECSPI1_IPG_GATE 51
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#define IMX5_CLK_ECSPI1_PER_GATE 52
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#define IMX5_CLK_ECSPI2_IPG_GATE 53
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#define IMX5_CLK_ECSPI2_PER_GATE 54
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#define IMX5_CLK_CSPI_IPG_GATE 55
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#define IMX5_CLK_SDMA_GATE 56
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#define IMX5_CLK_EMI_SLOW_GATE 57
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#define IMX5_CLK_IPU_SEL 58
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#define IMX5_CLK_IPU_GATE 59
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#define IMX5_CLK_NFC_GATE 60
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#define IMX5_CLK_IPU_DI1_GATE 61
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#define IMX5_CLK_VPU_SEL 62
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#define IMX5_CLK_VPU_GATE 63
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#define IMX5_CLK_VPU_REFERENCE_GATE 64
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#define IMX5_CLK_UART4_IPG_GATE 65
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#define IMX5_CLK_UART4_PER_GATE 66
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#define IMX5_CLK_UART5_IPG_GATE 67
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#define IMX5_CLK_UART5_PER_GATE 68
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#define IMX5_CLK_TVE_GATE 69
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#define IMX5_CLK_TVE_PRED 70
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#define IMX5_CLK_ESDHC1_PER_GATE 71
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#define IMX5_CLK_ESDHC2_PER_GATE 72
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#define IMX5_CLK_ESDHC3_PER_GATE 73
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#define IMX5_CLK_ESDHC4_PER_GATE 74
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#define IMX5_CLK_USB_PHY_GATE 75
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#define IMX5_CLK_HSI2C_GATE 76
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#define IMX5_CLK_MIPI_HSC1_GATE 77
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#define IMX5_CLK_MIPI_HSC2_GATE 78
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#define IMX5_CLK_MIPI_ESC_GATE 79
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#define IMX5_CLK_MIPI_HSP_GATE 80
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#define IMX5_CLK_LDB_DI1_DIV_3_5 81
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#define IMX5_CLK_LDB_DI1_DIV 82
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#define IMX5_CLK_LDB_DI0_DIV_3_5 83
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#define IMX5_CLK_LDB_DI0_DIV 84
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#define IMX5_CLK_LDB_DI1_GATE 85
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#define IMX5_CLK_CAN2_SERIAL_GATE 86
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#define IMX5_CLK_CAN2_IPG_GATE 87
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#define IMX5_CLK_I2C3_GATE 88
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#define IMX5_CLK_LP_APM 89
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#define IMX5_CLK_PERIPH_APM 90
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#define IMX5_CLK_MAIN_BUS 91
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#define IMX5_CLK_AHB_MAX 92
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#define IMX5_CLK_AIPS_TZ1 93
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#define IMX5_CLK_AIPS_TZ2 94
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#define IMX5_CLK_TMAX1 95
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#define IMX5_CLK_TMAX2 96
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#define IMX5_CLK_TMAX3 97
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#define IMX5_CLK_SPBA 98
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#define IMX5_CLK_UART_SEL 99
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#define IMX5_CLK_ESDHC_A_SEL 100
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#define IMX5_CLK_ESDHC_B_SEL 101
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#define IMX5_CLK_ESDHC_A_PODF 102
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#define IMX5_CLK_ESDHC_B_PODF 103
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#define IMX5_CLK_ECSPI_SEL 104
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#define IMX5_CLK_USBOH3_SEL 105
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#define IMX5_CLK_USB_PHY_SEL 106
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#define IMX5_CLK_IIM_GATE 107
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#define IMX5_CLK_USBOH3_GATE 108
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#define IMX5_CLK_EMI_FAST_GATE 109
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#define IMX5_CLK_IPU_DI0_GATE 110
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#define IMX5_CLK_GPC_DVFS 111
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#define IMX5_CLK_PLL1_SW 112
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#define IMX5_CLK_PLL2_SW 113
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#define IMX5_CLK_PLL3_SW 114
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#define IMX5_CLK_IPU_DI0_SEL 115
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#define IMX5_CLK_IPU_DI1_SEL 116
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#define IMX5_CLK_TVE_EXT_SEL 117
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#define IMX5_CLK_MX51_MIPI 118
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#define IMX5_CLK_PLL4_SW 119
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#define IMX5_CLK_LDB_DI1_SEL 120
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#define IMX5_CLK_DI_PLL4_PODF 121
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#define IMX5_CLK_LDB_DI0_SEL 122
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#define IMX5_CLK_LDB_DI0_GATE 123
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#define IMX5_CLK_USB_PHY1_GATE 124
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#define IMX5_CLK_USB_PHY2_GATE 125
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#define IMX5_CLK_PER_LP_APM 126
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#define IMX5_CLK_PER_PRED1 127
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#define IMX5_CLK_PER_PRED2 128
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#define IMX5_CLK_PER_PODF 129
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#define IMX5_CLK_PER_ROOT 130
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#define IMX5_CLK_SSI_APM 131
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#define IMX5_CLK_SSI1_ROOT_SEL 132
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#define IMX5_CLK_SSI2_ROOT_SEL 133
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#define IMX5_CLK_SSI3_ROOT_SEL 134
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#define IMX5_CLK_SSI_EXT1_SEL 135
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#define IMX5_CLK_SSI_EXT2_SEL 136
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#define IMX5_CLK_SSI_EXT1_COM_SEL 137
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#define IMX5_CLK_SSI_EXT2_COM_SEL 138
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#define IMX5_CLK_SSI1_ROOT_PRED 139
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#define IMX5_CLK_SSI1_ROOT_PODF 140
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#define IMX5_CLK_SSI2_ROOT_PRED 141
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#define IMX5_CLK_SSI2_ROOT_PODF 142
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#define IMX5_CLK_SSI_EXT1_PRED 143
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#define IMX5_CLK_SSI_EXT1_PODF 144
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#define IMX5_CLK_SSI_EXT2_PRED 145
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#define IMX5_CLK_SSI_EXT2_PODF 146
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#define IMX5_CLK_SSI1_ROOT_GATE 147
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#define IMX5_CLK_SSI2_ROOT_GATE 148
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#define IMX5_CLK_SSI3_ROOT_GATE 149
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#define IMX5_CLK_SSI_EXT1_GATE 150
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#define IMX5_CLK_SSI_EXT2_GATE 151
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#define IMX5_CLK_EPIT1_IPG_GATE 152
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#define IMX5_CLK_EPIT1_HF_GATE 153
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#define IMX5_CLK_EPIT2_IPG_GATE 154
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#define IMX5_CLK_EPIT2_HF_GATE 155
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#define IMX5_CLK_CAN_SEL 156
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#define IMX5_CLK_CAN1_SERIAL_GATE 157
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#define IMX5_CLK_CAN1_IPG_GATE 158
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#define IMX5_CLK_OWIRE_GATE 159
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#define IMX5_CLK_GPU3D_SEL 160
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#define IMX5_CLK_GPU2D_SEL 161
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#define IMX5_CLK_GPU3D_GATE 162
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#define IMX5_CLK_GPU2D_GATE 163
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#define IMX5_CLK_GARB_GATE 164
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#define IMX5_CLK_CKO1_SEL 165
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#define IMX5_CLK_CKO1_PODF 166
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#define IMX5_CLK_CKO1 167
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#define IMX5_CLK_CKO2_SEL 168
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#define IMX5_CLK_CKO2_PODF 169
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#define IMX5_CLK_CKO2 170
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#define IMX5_CLK_SRTC_GATE 171
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#define IMX5_CLK_PATA_GATE 172
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#define IMX5_CLK_SATA_GATE 173
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#define IMX5_CLK_SPDIF_XTAL_SEL 174
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#define IMX5_CLK_SPDIF0_SEL 175
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#define IMX5_CLK_SPDIF1_SEL 176
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#define IMX5_CLK_SPDIF0_PRED 177
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#define IMX5_CLK_SPDIF0_PODF 178
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#define IMX5_CLK_SPDIF1_PRED 179
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#define IMX5_CLK_SPDIF1_PODF 180
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#define IMX5_CLK_SPDIF0_COM_SEL 181
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#define IMX5_CLK_SPDIF1_COM_SEL 182
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#define IMX5_CLK_SPDIF0_GATE 183
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#define IMX5_CLK_SPDIF1_GATE 184
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#define IMX5_CLK_SPDIF_IPG_GATE 185
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#define IMX5_CLK_OCRAM 186
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#define IMX5_CLK_SAHARA_IPG_GATE 187
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#define IMX5_CLK_SATA_REF 188
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#define IMX5_CLK_STEP_SEL 189
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#define IMX5_CLK_CPU_PODF_SEL 190
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#define IMX5_CLK_ARM 191
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#define IMX5_CLK_FIRI_PRED 192
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#define IMX5_CLK_FIRI_SEL 193
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#define IMX5_CLK_FIRI_PODF 194
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#define IMX5_CLK_FIRI_SERIAL_GATE 195
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#define IMX5_CLK_FIRI_IPG_GATE 196
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#define IMX5_CLK_CSI0_MCLK1_PRED 197
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#define IMX5_CLK_CSI0_MCLK1_SEL 198
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#define IMX5_CLK_CSI0_MCLK1_PODF 199
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#define IMX5_CLK_CSI0_MCLK1_GATE 200
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#define IMX5_CLK_IEEE1588_PRED 201
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#define IMX5_CLK_IEEE1588_SEL 202
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#define IMX5_CLK_IEEE1588_PODF 203
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#define IMX5_CLK_IEEE1588_GATE 204
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#define IMX5_CLK_SCC2_IPG_GATE 205
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#define IMX5_CLK_END 206
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#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
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