mirror of https://gitee.com/openkylin/linux.git
1012 lines
23 KiB
C
1012 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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Samsung S5H1409 VSB/QAM demodulator driver
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Copyright (C) 2006 Steven Toth <stoth@linuxtv.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <media/dvb_frontend.h>
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#include "s5h1409.h"
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struct s5h1409_state {
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struct i2c_adapter *i2c;
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/* configuration settings */
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const struct s5h1409_config *config;
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struct dvb_frontend frontend;
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/* previous uncorrected block counter */
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enum fe_modulation current_modulation;
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u32 current_frequency;
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int if_freq;
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u32 is_qam_locked;
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/* QAM tuning state goes through the following state transitions */
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#define QAM_STATE_UNTUNED 0
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#define QAM_STATE_TUNING_STARTED 1
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#define QAM_STATE_INTERLEAVE_SET 2
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#define QAM_STATE_QAM_OPTIMIZED_L1 3
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#define QAM_STATE_QAM_OPTIMIZED_L2 4
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#define QAM_STATE_QAM_OPTIMIZED_L3 5
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u8 qam_state;
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};
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static int debug;
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "Enable verbose debug messages");
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#define dprintk if (debug) printk
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/* Register values to initialise the demod, this will set VSB by default */
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static struct init_tab {
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u8 reg;
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u16 data;
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} init_tab[] = {
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{ 0x00, 0x0071, },
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{ 0x01, 0x3213, },
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{ 0x09, 0x0025, },
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{ 0x1c, 0x001d, },
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{ 0x1f, 0x002d, },
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{ 0x20, 0x001d, },
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{ 0x22, 0x0022, },
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{ 0x23, 0x0020, },
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{ 0x29, 0x110f, },
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{ 0x2a, 0x10b4, },
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{ 0x2b, 0x10ae, },
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{ 0x2c, 0x0031, },
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{ 0x31, 0x010d, },
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{ 0x32, 0x0100, },
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{ 0x44, 0x0510, },
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{ 0x54, 0x0104, },
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{ 0x58, 0x2222, },
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{ 0x59, 0x1162, },
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{ 0x5a, 0x3211, },
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{ 0x5d, 0x0370, },
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{ 0x5e, 0x0296, },
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{ 0x61, 0x0010, },
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{ 0x63, 0x4a00, },
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{ 0x65, 0x0800, },
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{ 0x71, 0x0003, },
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{ 0x72, 0x0470, },
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{ 0x81, 0x0002, },
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{ 0x82, 0x0600, },
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{ 0x86, 0x0002, },
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{ 0x8a, 0x2c38, },
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{ 0x8b, 0x2a37, },
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{ 0x92, 0x302f, },
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{ 0x93, 0x3332, },
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{ 0x96, 0x000c, },
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{ 0x99, 0x0101, },
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{ 0x9c, 0x2e37, },
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{ 0x9d, 0x2c37, },
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{ 0x9e, 0x2c37, },
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{ 0xab, 0x0100, },
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{ 0xac, 0x1003, },
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{ 0xad, 0x103f, },
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{ 0xe2, 0x0100, },
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{ 0xe3, 0x1000, },
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{ 0x28, 0x1010, },
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{ 0xb1, 0x000e, },
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};
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/* VSB SNR lookup table */
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static struct vsb_snr_tab {
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u16 val;
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u16 data;
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} vsb_snr_tab[] = {
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{ 924, 300, },
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{ 923, 300, },
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{ 918, 295, },
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{ 915, 290, },
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{ 911, 285, },
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{ 906, 280, },
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{ 901, 275, },
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{ 896, 270, },
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{ 891, 265, },
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{ 885, 260, },
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{ 879, 255, },
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{ 873, 250, },
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{ 864, 245, },
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{ 858, 240, },
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{ 850, 235, },
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{ 841, 230, },
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{ 832, 225, },
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{ 823, 220, },
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{ 812, 215, },
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{ 802, 210, },
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{ 788, 205, },
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{ 778, 200, },
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{ 767, 195, },
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{ 753, 190, },
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{ 740, 185, },
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{ 725, 180, },
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{ 707, 175, },
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{ 689, 170, },
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{ 671, 165, },
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{ 656, 160, },
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{ 637, 155, },
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{ 616, 150, },
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{ 542, 145, },
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{ 519, 140, },
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{ 507, 135, },
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{ 497, 130, },
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{ 492, 125, },
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{ 474, 120, },
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{ 300, 111, },
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{ 0, 0, },
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};
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/* QAM64 SNR lookup table */
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static struct qam64_snr_tab {
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u16 val;
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u16 data;
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} qam64_snr_tab[] = {
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{ 1, 0, },
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{ 12, 300, },
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{ 15, 290, },
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{ 18, 280, },
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{ 22, 270, },
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{ 23, 268, },
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{ 24, 266, },
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{ 25, 264, },
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{ 27, 262, },
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{ 28, 260, },
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{ 29, 258, },
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{ 30, 256, },
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{ 32, 254, },
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{ 33, 252, },
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{ 34, 250, },
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{ 35, 249, },
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{ 36, 248, },
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{ 37, 247, },
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{ 38, 246, },
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{ 39, 245, },
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{ 40, 244, },
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{ 41, 243, },
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{ 42, 241, },
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{ 43, 240, },
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{ 44, 239, },
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{ 45, 238, },
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{ 46, 237, },
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{ 47, 236, },
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{ 48, 235, },
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{ 49, 234, },
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{ 50, 233, },
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{ 51, 232, },
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{ 52, 231, },
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{ 53, 230, },
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{ 55, 229, },
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{ 56, 228, },
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{ 57, 227, },
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{ 58, 226, },
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{ 59, 225, },
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{ 60, 224, },
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{ 62, 223, },
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{ 63, 222, },
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{ 65, 221, },
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{ 66, 220, },
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{ 68, 219, },
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{ 69, 218, },
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{ 70, 217, },
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{ 72, 216, },
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{ 73, 215, },
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{ 75, 214, },
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{ 76, 213, },
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{ 78, 212, },
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{ 80, 211, },
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{ 81, 210, },
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{ 83, 209, },
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{ 84, 208, },
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{ 85, 207, },
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{ 87, 206, },
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{ 89, 205, },
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{ 91, 204, },
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{ 93, 203, },
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{ 95, 202, },
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{ 96, 201, },
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{ 104, 200, },
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{ 255, 0, },
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};
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/* QAM256 SNR lookup table */
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static struct qam256_snr_tab {
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u16 val;
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u16 data;
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} qam256_snr_tab[] = {
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{ 1, 0, },
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{ 12, 400, },
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{ 13, 390, },
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{ 15, 380, },
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{ 17, 360, },
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{ 19, 350, },
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{ 22, 348, },
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{ 23, 346, },
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{ 24, 344, },
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{ 25, 342, },
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{ 26, 340, },
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{ 27, 336, },
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{ 28, 334, },
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{ 29, 332, },
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{ 30, 330, },
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{ 31, 328, },
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{ 32, 326, },
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{ 33, 325, },
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{ 34, 322, },
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{ 35, 320, },
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{ 37, 318, },
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{ 39, 316, },
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{ 40, 314, },
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{ 41, 312, },
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{ 42, 310, },
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{ 43, 308, },
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{ 46, 306, },
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{ 47, 304, },
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{ 49, 302, },
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{ 51, 300, },
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{ 53, 298, },
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{ 54, 297, },
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{ 55, 296, },
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{ 56, 295, },
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{ 57, 294, },
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{ 59, 293, },
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{ 60, 292, },
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{ 61, 291, },
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{ 63, 290, },
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{ 64, 289, },
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{ 65, 288, },
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{ 66, 287, },
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{ 68, 286, },
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{ 69, 285, },
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{ 71, 284, },
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{ 72, 283, },
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{ 74, 282, },
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{ 75, 281, },
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{ 76, 280, },
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{ 77, 279, },
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{ 78, 278, },
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{ 81, 277, },
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{ 83, 276, },
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{ 84, 275, },
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{ 86, 274, },
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{ 87, 273, },
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{ 89, 272, },
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{ 90, 271, },
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{ 92, 270, },
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{ 93, 269, },
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{ 95, 268, },
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{ 96, 267, },
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{ 98, 266, },
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{ 100, 265, },
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{ 102, 264, },
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{ 104, 263, },
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{ 105, 262, },
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{ 106, 261, },
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{ 110, 260, },
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{ 255, 0, },
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};
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/* 8 bit registers, 16 bit values */
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static int s5h1409_writereg(struct s5h1409_state *state, u8 reg, u16 data)
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{
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int ret;
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u8 buf[] = { reg, data >> 8, data & 0xff };
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struct i2c_msg msg = { .addr = state->config->demod_address,
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.flags = 0, .buf = buf, .len = 3 };
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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printk(KERN_ERR "%s: error (reg == 0x%02x, val == 0x%04x, ret == %i)\n",
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__func__, reg, data, ret);
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return (ret != 1) ? -1 : 0;
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}
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static u16 s5h1409_readreg(struct s5h1409_state *state, u8 reg)
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{
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int ret;
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u8 b0[] = { reg };
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u8 b1[] = { 0, 0 };
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struct i2c_msg msg[] = {
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{ .addr = state->config->demod_address, .flags = 0,
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.buf = b0, .len = 1 },
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{ .addr = state->config->demod_address, .flags = I2C_M_RD,
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.buf = b1, .len = 2 } };
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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printk("%s: readreg error (ret == %i)\n", __func__, ret);
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return (b1[0] << 8) | b1[1];
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}
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static int s5h1409_softreset(struct dvb_frontend *fe)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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dprintk("%s()\n", __func__);
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s5h1409_writereg(state, 0xf5, 0);
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s5h1409_writereg(state, 0xf5, 1);
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state->is_qam_locked = 0;
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state->qam_state = QAM_STATE_UNTUNED;
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return 0;
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}
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#define S5H1409_VSB_IF_FREQ 5380
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#define S5H1409_QAM_IF_FREQ (state->config->qam_if)
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static int s5h1409_set_if_freq(struct dvb_frontend *fe, int KHz)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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dprintk("%s(%d KHz)\n", __func__, KHz);
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switch (KHz) {
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case 4000:
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s5h1409_writereg(state, 0x87, 0x014b);
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s5h1409_writereg(state, 0x88, 0x0cb5);
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s5h1409_writereg(state, 0x89, 0x03e2);
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break;
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case 5380:
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case 44000:
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default:
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s5h1409_writereg(state, 0x87, 0x01be);
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s5h1409_writereg(state, 0x88, 0x0436);
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s5h1409_writereg(state, 0x89, 0x054d);
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break;
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}
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state->if_freq = KHz;
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return 0;
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}
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static int s5h1409_set_spectralinversion(struct dvb_frontend *fe, int inverted)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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dprintk("%s(%d)\n", __func__, inverted);
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if (inverted == 1)
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return s5h1409_writereg(state, 0x1b, 0x1101); /* Inverted */
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else
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return s5h1409_writereg(state, 0x1b, 0x0110); /* Normal */
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}
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static int s5h1409_enable_modulation(struct dvb_frontend *fe,
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enum fe_modulation m)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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dprintk("%s(0x%08x)\n", __func__, m);
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switch (m) {
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case VSB_8:
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dprintk("%s() VSB_8\n", __func__);
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if (state->if_freq != S5H1409_VSB_IF_FREQ)
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s5h1409_set_if_freq(fe, S5H1409_VSB_IF_FREQ);
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s5h1409_writereg(state, 0xf4, 0);
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break;
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case QAM_64:
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case QAM_256:
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case QAM_AUTO:
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dprintk("%s() QAM_AUTO (64/256)\n", __func__);
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if (state->if_freq != S5H1409_QAM_IF_FREQ)
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s5h1409_set_if_freq(fe, S5H1409_QAM_IF_FREQ);
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s5h1409_writereg(state, 0xf4, 1);
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s5h1409_writereg(state, 0x85, 0x110);
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break;
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default:
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dprintk("%s() Invalid modulation\n", __func__);
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return -EINVAL;
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}
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state->current_modulation = m;
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s5h1409_softreset(fe);
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return 0;
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}
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static int s5h1409_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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dprintk("%s(%d)\n", __func__, enable);
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if (enable)
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return s5h1409_writereg(state, 0xf3, 1);
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else
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return s5h1409_writereg(state, 0xf3, 0);
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}
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static int s5h1409_set_gpio(struct dvb_frontend *fe, int enable)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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dprintk("%s(%d)\n", __func__, enable);
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if (enable)
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return s5h1409_writereg(state, 0xe3,
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s5h1409_readreg(state, 0xe3) | 0x1100);
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else
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return s5h1409_writereg(state, 0xe3,
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s5h1409_readreg(state, 0xe3) & 0xfeff);
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}
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static int s5h1409_sleep(struct dvb_frontend *fe, int enable)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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dprintk("%s(%d)\n", __func__, enable);
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return s5h1409_writereg(state, 0xf2, enable);
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}
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static int s5h1409_register_reset(struct dvb_frontend *fe)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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dprintk("%s()\n", __func__);
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return s5h1409_writereg(state, 0xfa, 0);
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}
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static void s5h1409_set_qam_amhum_mode(struct dvb_frontend *fe)
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{
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struct s5h1409_state *state = fe->demodulator_priv;
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u16 reg;
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if (state->qam_state < QAM_STATE_INTERLEAVE_SET) {
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/* We should not perform amhum optimization until
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the interleave mode has been configured */
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return;
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}
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if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) {
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/* We've already reached the maximum optimization level, so
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don't bother banging on the status registers */
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return;
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}
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/* QAM EQ lock check */
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reg = s5h1409_readreg(state, 0xf0);
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if ((reg >> 13) & 0x1) {
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reg &= 0xff;
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s5h1409_writereg(state, 0x96, 0x000c);
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if (reg < 0x68) {
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if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) {
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dprintk("%s() setting QAM state to OPT_L3\n",
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__func__);
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s5h1409_writereg(state, 0x93, 0x3130);
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s5h1409_writereg(state, 0x9e, 0x2836);
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state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3;
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}
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} else {
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if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) {
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dprintk("%s() setting QAM state to OPT_L2\n",
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__func__);
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s5h1409_writereg(state, 0x93, 0x3332);
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s5h1409_writereg(state, 0x9e, 0x2c37);
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state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2;
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}
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}
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} else {
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if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) {
|
|
dprintk("%s() setting QAM state to OPT_L1\n", __func__);
|
|
s5h1409_writereg(state, 0x96, 0x0008);
|
|
s5h1409_writereg(state, 0x93, 0x3332);
|
|
s5h1409_writereg(state, 0x9e, 0x2c37);
|
|
state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void s5h1409_set_qam_amhum_mode_legacy(struct dvb_frontend *fe)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
u16 reg;
|
|
|
|
if (state->is_qam_locked)
|
|
return;
|
|
|
|
/* QAM EQ lock check */
|
|
reg = s5h1409_readreg(state, 0xf0);
|
|
|
|
if ((reg >> 13) & 0x1) {
|
|
|
|
state->is_qam_locked = 1;
|
|
reg &= 0xff;
|
|
|
|
s5h1409_writereg(state, 0x96, 0x00c);
|
|
if ((reg < 0x38) || (reg > 0x68)) {
|
|
s5h1409_writereg(state, 0x93, 0x3332);
|
|
s5h1409_writereg(state, 0x9e, 0x2c37);
|
|
} else {
|
|
s5h1409_writereg(state, 0x93, 0x3130);
|
|
s5h1409_writereg(state, 0x9e, 0x2836);
|
|
}
|
|
|
|
} else {
|
|
s5h1409_writereg(state, 0x96, 0x0008);
|
|
s5h1409_writereg(state, 0x93, 0x3332);
|
|
s5h1409_writereg(state, 0x9e, 0x2c37);
|
|
}
|
|
}
|
|
|
|
static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
u16 reg, reg1, reg2;
|
|
|
|
if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) {
|
|
/* We've done the optimization already */
|
|
return;
|
|
}
|
|
|
|
reg = s5h1409_readreg(state, 0xf1);
|
|
|
|
/* Master lock */
|
|
if ((reg >> 15) & 0x1) {
|
|
if (state->qam_state == QAM_STATE_UNTUNED ||
|
|
state->qam_state == QAM_STATE_TUNING_STARTED) {
|
|
dprintk("%s() setting QAM state to INTERLEAVE_SET\n",
|
|
__func__);
|
|
reg1 = s5h1409_readreg(state, 0xb2);
|
|
reg2 = s5h1409_readreg(state, 0xad);
|
|
|
|
s5h1409_writereg(state, 0x96, 0x0020);
|
|
s5h1409_writereg(state, 0xad,
|
|
(((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
|
|
state->qam_state = QAM_STATE_INTERLEAVE_SET;
|
|
}
|
|
} else {
|
|
if (state->qam_state == QAM_STATE_UNTUNED) {
|
|
dprintk("%s() setting QAM state to TUNING_STARTED\n",
|
|
__func__);
|
|
s5h1409_writereg(state, 0x96, 0x08);
|
|
s5h1409_writereg(state, 0xab,
|
|
s5h1409_readreg(state, 0xab) | 0x1001);
|
|
state->qam_state = QAM_STATE_TUNING_STARTED;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void s5h1409_set_qam_interleave_mode_legacy(struct dvb_frontend *fe)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
u16 reg, reg1, reg2;
|
|
|
|
reg = s5h1409_readreg(state, 0xf1);
|
|
|
|
/* Master lock */
|
|
if ((reg >> 15) & 0x1) {
|
|
if (state->qam_state != 2) {
|
|
state->qam_state = 2;
|
|
reg1 = s5h1409_readreg(state, 0xb2);
|
|
reg2 = s5h1409_readreg(state, 0xad);
|
|
|
|
s5h1409_writereg(state, 0x96, 0x20);
|
|
s5h1409_writereg(state, 0xad,
|
|
(((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
|
|
s5h1409_writereg(state, 0xab,
|
|
s5h1409_readreg(state, 0xab) & 0xeffe);
|
|
}
|
|
} else {
|
|
if (state->qam_state != 1) {
|
|
state->qam_state = 1;
|
|
s5h1409_writereg(state, 0x96, 0x08);
|
|
s5h1409_writereg(state, 0xab,
|
|
s5h1409_readreg(state, 0xab) | 0x1001);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
|
|
static int s5h1409_set_frontend(struct dvb_frontend *fe)
|
|
{
|
|
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
|
|
dprintk("%s(frequency=%d)\n", __func__, p->frequency);
|
|
|
|
s5h1409_softreset(fe);
|
|
|
|
state->current_frequency = p->frequency;
|
|
|
|
s5h1409_enable_modulation(fe, p->modulation);
|
|
|
|
if (fe->ops.tuner_ops.set_params) {
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
fe->ops.i2c_gate_ctrl(fe, 1);
|
|
fe->ops.tuner_ops.set_params(fe);
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
fe->ops.i2c_gate_ctrl(fe, 0);
|
|
}
|
|
|
|
/* Issue a reset to the demod so it knows to resync against the
|
|
newly tuned frequency */
|
|
s5h1409_softreset(fe);
|
|
|
|
/* Optimize the demod for QAM */
|
|
if (state->current_modulation != VSB_8) {
|
|
/* This almost certainly applies to all boards, but for now
|
|
only do it for the HVR-1600. Once the other boards are
|
|
tested, the "legacy" versions can just go away */
|
|
if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
|
|
s5h1409_set_qam_interleave_mode(fe);
|
|
s5h1409_set_qam_amhum_mode(fe);
|
|
} else {
|
|
s5h1409_set_qam_amhum_mode_legacy(fe);
|
|
s5h1409_set_qam_interleave_mode_legacy(fe);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s5h1409_set_mpeg_timing(struct dvb_frontend *fe, int mode)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
u16 val;
|
|
|
|
dprintk("%s(%d)\n", __func__, mode);
|
|
|
|
val = s5h1409_readreg(state, 0xac) & 0xcfff;
|
|
switch (mode) {
|
|
case S5H1409_MPEGTIMING_CONTINUOUS_INVERTING_CLOCK:
|
|
val |= 0x0000;
|
|
break;
|
|
case S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK:
|
|
dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
|
|
val |= 0x1000;
|
|
break;
|
|
case S5H1409_MPEGTIMING_NONCONTINUOUS_INVERTING_CLOCK:
|
|
val |= 0x2000;
|
|
break;
|
|
case S5H1409_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK:
|
|
val |= 0x3000;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Configure MPEG Signal Timing charactistics */
|
|
return s5h1409_writereg(state, 0xac, val);
|
|
}
|
|
|
|
/* Reset the demod hardware and reset all of the configuration registers
|
|
to a default state. */
|
|
static int s5h1409_init(struct dvb_frontend *fe)
|
|
{
|
|
int i;
|
|
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
dprintk("%s()\n", __func__);
|
|
|
|
s5h1409_sleep(fe, 0);
|
|
s5h1409_register_reset(fe);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(init_tab); i++)
|
|
s5h1409_writereg(state, init_tab[i].reg, init_tab[i].data);
|
|
|
|
/* The datasheet says that after initialisation, VSB is default */
|
|
state->current_modulation = VSB_8;
|
|
|
|
/* Optimize for the HVR-1600 if appropriate. Note that some of these
|
|
may get folded into the generic case after testing with other
|
|
devices */
|
|
if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
|
|
/* VSB AGC REF */
|
|
s5h1409_writereg(state, 0x09, 0x0050);
|
|
|
|
/* Unknown but Windows driver does it... */
|
|
s5h1409_writereg(state, 0x21, 0x0001);
|
|
s5h1409_writereg(state, 0x50, 0x030e);
|
|
|
|
/* QAM AGC REF */
|
|
s5h1409_writereg(state, 0x82, 0x0800);
|
|
}
|
|
|
|
if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
|
|
s5h1409_writereg(state, 0xab,
|
|
s5h1409_readreg(state, 0xab) | 0x100); /* Serial */
|
|
else
|
|
s5h1409_writereg(state, 0xab,
|
|
s5h1409_readreg(state, 0xab) & 0xfeff); /* Parallel */
|
|
|
|
s5h1409_set_spectralinversion(fe, state->config->inversion);
|
|
s5h1409_set_if_freq(fe, state->if_freq);
|
|
s5h1409_set_gpio(fe, state->config->gpio);
|
|
s5h1409_set_mpeg_timing(fe, state->config->mpeg_timing);
|
|
s5h1409_softreset(fe);
|
|
|
|
/* Note: Leaving the I2C gate closed. */
|
|
s5h1409_i2c_gate_ctrl(fe, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s5h1409_read_status(struct dvb_frontend *fe, enum fe_status *status)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
u16 reg;
|
|
u32 tuner_status = 0;
|
|
|
|
*status = 0;
|
|
|
|
/* Optimize the demod for QAM */
|
|
if (state->current_modulation != VSB_8) {
|
|
/* This almost certainly applies to all boards, but for now
|
|
only do it for the HVR-1600. Once the other boards are
|
|
tested, the "legacy" versions can just go away */
|
|
if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
|
|
s5h1409_set_qam_interleave_mode(fe);
|
|
s5h1409_set_qam_amhum_mode(fe);
|
|
}
|
|
}
|
|
|
|
/* Get the demodulator status */
|
|
reg = s5h1409_readreg(state, 0xf1);
|
|
if (reg & 0x1000)
|
|
*status |= FE_HAS_VITERBI;
|
|
if (reg & 0x8000)
|
|
*status |= FE_HAS_LOCK | FE_HAS_SYNC;
|
|
|
|
switch (state->config->status_mode) {
|
|
case S5H1409_DEMODLOCKING:
|
|
if (*status & FE_HAS_VITERBI)
|
|
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
|
|
break;
|
|
case S5H1409_TUNERLOCKING:
|
|
/* Get the tuner status */
|
|
if (fe->ops.tuner_ops.get_status) {
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
fe->ops.i2c_gate_ctrl(fe, 1);
|
|
|
|
fe->ops.tuner_ops.get_status(fe, &tuner_status);
|
|
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
fe->ops.i2c_gate_ctrl(fe, 0);
|
|
}
|
|
if (tuner_status)
|
|
*status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
|
|
break;
|
|
}
|
|
|
|
dprintk("%s() status 0x%08x\n", __func__, *status);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s5h1409_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
|
|
{
|
|
int i, ret = -EINVAL;
|
|
dprintk("%s()\n", __func__);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
|
|
if (v < qam256_snr_tab[i].val) {
|
|
*snr = qam256_snr_tab[i].data;
|
|
ret = 0;
|
|
break;
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int s5h1409_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
|
|
{
|
|
int i, ret = -EINVAL;
|
|
dprintk("%s()\n", __func__);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
|
|
if (v < qam64_snr_tab[i].val) {
|
|
*snr = qam64_snr_tab[i].data;
|
|
ret = 0;
|
|
break;
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int s5h1409_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
|
|
{
|
|
int i, ret = -EINVAL;
|
|
dprintk("%s()\n", __func__);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
|
|
if (v > vsb_snr_tab[i].val) {
|
|
*snr = vsb_snr_tab[i].data;
|
|
ret = 0;
|
|
break;
|
|
}
|
|
}
|
|
dprintk("%s() snr=%d\n", __func__, *snr);
|
|
return ret;
|
|
}
|
|
|
|
static int s5h1409_read_snr(struct dvb_frontend *fe, u16 *snr)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
u16 reg;
|
|
dprintk("%s()\n", __func__);
|
|
|
|
switch (state->current_modulation) {
|
|
case QAM_64:
|
|
reg = s5h1409_readreg(state, 0xf0) & 0xff;
|
|
return s5h1409_qam64_lookup_snr(fe, snr, reg);
|
|
case QAM_256:
|
|
reg = s5h1409_readreg(state, 0xf0) & 0xff;
|
|
return s5h1409_qam256_lookup_snr(fe, snr, reg);
|
|
case VSB_8:
|
|
reg = s5h1409_readreg(state, 0xf1) & 0x3ff;
|
|
return s5h1409_vsb_lookup_snr(fe, snr, reg);
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int s5h1409_read_signal_strength(struct dvb_frontend *fe,
|
|
u16 *signal_strength)
|
|
{
|
|
/* borrowed from lgdt330x.c
|
|
*
|
|
* Calculate strength from SNR up to 35dB
|
|
* Even though the SNR can go higher than 35dB,
|
|
* there is some comfort factor in having a range of
|
|
* strong signals that can show at 100%
|
|
*/
|
|
u16 snr;
|
|
u32 tmp;
|
|
int ret = s5h1409_read_snr(fe, &snr);
|
|
|
|
*signal_strength = 0;
|
|
|
|
if (0 == ret) {
|
|
/* The following calculation method was chosen
|
|
* purely for the sake of code re-use from the
|
|
* other demod drivers that use this method */
|
|
|
|
/* Convert from SNR in dB * 10 to 8.24 fixed-point */
|
|
tmp = (snr * ((1 << 24) / 10));
|
|
|
|
/* Convert from 8.24 fixed-point to
|
|
* scale the range 0 - 35*2^24 into 0 - 65535*/
|
|
if (tmp >= 8960 * 0x10000)
|
|
*signal_strength = 0xffff;
|
|
else
|
|
*signal_strength = tmp / 8960;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int s5h1409_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
|
|
*ucblocks = s5h1409_readreg(state, 0xb5);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s5h1409_read_ber(struct dvb_frontend *fe, u32 *ber)
|
|
{
|
|
return s5h1409_read_ucblocks(fe, ber);
|
|
}
|
|
|
|
static int s5h1409_get_frontend(struct dvb_frontend *fe,
|
|
struct dtv_frontend_properties *p)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
|
|
p->frequency = state->current_frequency;
|
|
p->modulation = state->current_modulation;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s5h1409_get_tune_settings(struct dvb_frontend *fe,
|
|
struct dvb_frontend_tune_settings *tune)
|
|
{
|
|
tune->min_delay_ms = 1000;
|
|
return 0;
|
|
}
|
|
|
|
static void s5h1409_release(struct dvb_frontend *fe)
|
|
{
|
|
struct s5h1409_state *state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static const struct dvb_frontend_ops s5h1409_ops;
|
|
|
|
struct dvb_frontend *s5h1409_attach(const struct s5h1409_config *config,
|
|
struct i2c_adapter *i2c)
|
|
{
|
|
struct s5h1409_state *state = NULL;
|
|
u16 reg;
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct s5h1409_state), GFP_KERNEL);
|
|
if (state == NULL)
|
|
goto error;
|
|
|
|
/* setup the state */
|
|
state->config = config;
|
|
state->i2c = i2c;
|
|
state->current_modulation = 0;
|
|
state->if_freq = S5H1409_VSB_IF_FREQ;
|
|
|
|
/* check if the demod exists */
|
|
reg = s5h1409_readreg(state, 0x04);
|
|
if ((reg != 0x0066) && (reg != 0x007f))
|
|
goto error;
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&state->frontend.ops, &s5h1409_ops,
|
|
sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
|
|
if (s5h1409_init(&state->frontend) != 0) {
|
|
printk(KERN_ERR "%s: Failed to initialize correctly\n",
|
|
__func__);
|
|
goto error;
|
|
}
|
|
|
|
/* Note: Leaving the I2C gate open here. */
|
|
s5h1409_i2c_gate_ctrl(&state->frontend, 1);
|
|
|
|
return &state->frontend;
|
|
|
|
error:
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL(s5h1409_attach);
|
|
|
|
static const struct dvb_frontend_ops s5h1409_ops = {
|
|
.delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
|
|
.info = {
|
|
.name = "Samsung S5H1409 QAM/8VSB Frontend",
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.frequency_min_hz = 54 * MHz,
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.frequency_max_hz = 858 * MHz,
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.frequency_stepsize_hz = 62500,
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.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
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},
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.init = s5h1409_init,
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.i2c_gate_ctrl = s5h1409_i2c_gate_ctrl,
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.set_frontend = s5h1409_set_frontend,
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.get_frontend = s5h1409_get_frontend,
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.get_tune_settings = s5h1409_get_tune_settings,
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.read_status = s5h1409_read_status,
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.read_ber = s5h1409_read_ber,
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.read_signal_strength = s5h1409_read_signal_strength,
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.read_snr = s5h1409_read_snr,
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.read_ucblocks = s5h1409_read_ucblocks,
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.release = s5h1409_release,
|
|
};
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|
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MODULE_DESCRIPTION("Samsung S5H1409 QAM-B/ATSC Demodulator driver");
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MODULE_AUTHOR("Steven Toth");
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MODULE_LICENSE("GPL");
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