mirror of https://gitee.com/openkylin/linux.git
548 lines
14 KiB
C
548 lines
14 KiB
C
/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License as published by the Free Software Foundation;
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* either version 2, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
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* the implied warranty of MERCHANTABILITY or FITNESS FOR
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* A PARTICULAR PURPOSE.See the GNU General Public License
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* for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/via-core.h>
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#include "global.h"
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/*
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* Figure out an appropriate bytes-per-pixel setting.
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*/
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static int viafb_set_bpp(void __iomem *engine, u8 bpp)
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{
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u32 gemode;
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/* Preserve the reserved bits */
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/* Lowest 2 bits to zero gives us no rotation */
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gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
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switch (bpp) {
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case 8:
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gemode |= VIA_GEM_8bpp;
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break;
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case 16:
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gemode |= VIA_GEM_16bpp;
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break;
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case 32:
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gemode |= VIA_GEM_32bpp;
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break;
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default:
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printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
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return -EINVAL;
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}
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writel(gemode, engine + VIA_REG_GEMODE);
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return 0;
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}
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static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
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u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
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u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
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u32 fg_color, u32 bg_color, u8 fill_rop)
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{
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u32 ge_cmd = 0, tmp, i;
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int ret;
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if (!op || op > 3) {
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printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
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return -EINVAL;
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}
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if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
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if (src_x < dst_x) {
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ge_cmd |= 0x00008000;
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src_x += width - 1;
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dst_x += width - 1;
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}
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if (src_y < dst_y) {
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ge_cmd |= 0x00004000;
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src_y += height - 1;
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dst_y += height - 1;
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}
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}
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if (op == VIA_BITBLT_FILL) {
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switch (fill_rop) {
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case 0x00: /* blackness */
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case 0x5A: /* pattern inversion */
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case 0xF0: /* pattern copy */
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case 0xFF: /* whiteness */
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break;
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default:
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printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
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"%u\n", fill_rop);
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return -EINVAL;
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}
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}
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ret = viafb_set_bpp(engine, dst_bpp);
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if (ret)
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return ret;
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if (op != VIA_BITBLT_FILL) {
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if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
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|| src_y & 0xFFFFF000) {
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printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
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"x/y %d %d\n", src_x, src_y);
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return -EINVAL;
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}
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tmp = src_x | (src_y << 16);
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writel(tmp, engine + 0x08);
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}
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if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
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printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
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"%d %d\n", dst_x, dst_y);
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return -EINVAL;
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}
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tmp = dst_x | (dst_y << 16);
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writel(tmp, engine + 0x0C);
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if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
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printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
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"%d %d\n", width, height);
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return -EINVAL;
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}
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tmp = (width - 1) | ((height - 1) << 16);
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writel(tmp, engine + 0x10);
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if (op != VIA_BITBLT_COLOR)
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writel(fg_color, engine + 0x18);
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if (op == VIA_BITBLT_MONO)
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writel(bg_color, engine + 0x1C);
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if (op != VIA_BITBLT_FILL) {
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tmp = src_mem ? 0 : src_addr;
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if (dst_addr & 0xE0000007) {
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printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
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"address %X\n", tmp);
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return -EINVAL;
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}
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tmp >>= 3;
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writel(tmp, engine + 0x30);
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}
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if (dst_addr & 0xE0000007) {
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printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
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"address %X\n", dst_addr);
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return -EINVAL;
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}
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tmp = dst_addr >> 3;
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writel(tmp, engine + 0x34);
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if (op == VIA_BITBLT_FILL)
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tmp = 0;
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else
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tmp = src_pitch;
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if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
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printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
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tmp, dst_pitch);
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return -EINVAL;
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}
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tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3));
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writel(tmp, engine + 0x38);
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if (op == VIA_BITBLT_FILL)
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ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
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else {
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ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
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if (src_mem)
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ge_cmd |= 0x00000040;
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if (op == VIA_BITBLT_MONO)
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ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
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else
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ge_cmd |= 0x00000001;
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}
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writel(ge_cmd, engine);
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if (op == VIA_BITBLT_FILL || !src_mem)
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return 0;
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tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
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3) >> 2;
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for (i = 0; i < tmp; i++)
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writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
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return 0;
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}
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static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
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u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
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u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
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u32 fg_color, u32 bg_color, u8 fill_rop)
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{
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u32 ge_cmd = 0, tmp, i;
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int ret;
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if (!op || op > 3) {
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printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
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return -EINVAL;
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}
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if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
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if (src_x < dst_x) {
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ge_cmd |= 0x00008000;
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src_x += width - 1;
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dst_x += width - 1;
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}
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if (src_y < dst_y) {
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ge_cmd |= 0x00004000;
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src_y += height - 1;
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dst_y += height - 1;
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}
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}
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if (op == VIA_BITBLT_FILL) {
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switch (fill_rop) {
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case 0x00: /* blackness */
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case 0x5A: /* pattern inversion */
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case 0xF0: /* pattern copy */
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case 0xFF: /* whiteness */
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break;
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default:
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printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
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"%u\n", fill_rop);
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return -EINVAL;
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}
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}
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ret = viafb_set_bpp(engine, dst_bpp);
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if (ret)
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return ret;
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if (op == VIA_BITBLT_FILL)
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tmp = 0;
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else
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tmp = src_pitch;
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if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
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printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
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tmp, dst_pitch);
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return -EINVAL;
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}
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tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
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writel(tmp, engine + 0x08);
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if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
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printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
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"%d %d\n", width, height);
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return -EINVAL;
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}
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tmp = (width - 1) | ((height - 1) << 16);
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writel(tmp, engine + 0x0C);
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if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
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printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
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"%d %d\n", dst_x, dst_y);
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return -EINVAL;
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}
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tmp = dst_x | (dst_y << 16);
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writel(tmp, engine + 0x10);
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if (dst_addr & 0xE0000007) {
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printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
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"address %X\n", dst_addr);
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return -EINVAL;
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}
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tmp = dst_addr >> 3;
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writel(tmp, engine + 0x14);
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if (op != VIA_BITBLT_FILL) {
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if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
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|| src_y & 0xFFFFF000) {
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printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
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"x/y %d %d\n", src_x, src_y);
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return -EINVAL;
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}
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tmp = src_x | (src_y << 16);
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writel(tmp, engine + 0x18);
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tmp = src_mem ? 0 : src_addr;
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if (dst_addr & 0xE0000007) {
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printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
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"address %X\n", tmp);
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return -EINVAL;
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}
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tmp >>= 3;
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writel(tmp, engine + 0x1C);
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}
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if (op == VIA_BITBLT_FILL) {
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writel(fg_color, engine + 0x58);
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} else if (op == VIA_BITBLT_MONO) {
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writel(fg_color, engine + 0x4C);
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writel(bg_color, engine + 0x50);
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}
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if (op == VIA_BITBLT_FILL)
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ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
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else {
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ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
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if (src_mem)
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ge_cmd |= 0x00000040;
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if (op == VIA_BITBLT_MONO)
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ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
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else
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ge_cmd |= 0x00000001;
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}
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writel(ge_cmd, engine);
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if (op == VIA_BITBLT_FILL || !src_mem)
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return 0;
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tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
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3) >> 2;
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for (i = 0; i < tmp; i++)
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writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
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return 0;
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}
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int viafb_setup_engine(struct fb_info *info)
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{
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struct viafb_par *viapar = info->par;
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void __iomem *engine;
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u32 chip_name = viapar->shared->chip_info.gfx_chip_name;
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engine = viapar->shared->vdev->engine_mmio;
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if (!engine) {
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printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
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"hardware acceleration disabled\n");
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return -ENOMEM;
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}
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switch (chip_name) {
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case UNICHROME_CLE266:
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case UNICHROME_K400:
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case UNICHROME_K800:
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case UNICHROME_PM800:
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case UNICHROME_CN700:
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case UNICHROME_CX700:
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case UNICHROME_CN750:
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case UNICHROME_K8M890:
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case UNICHROME_P4M890:
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case UNICHROME_P4M900:
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viapar->shared->hw_bitblt = hw_bitblt_1;
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break;
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case UNICHROME_VX800:
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case UNICHROME_VX855:
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case UNICHROME_VX900:
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viapar->shared->hw_bitblt = hw_bitblt_2;
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break;
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default:
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viapar->shared->hw_bitblt = NULL;
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}
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viapar->fbmem_free -= CURSOR_SIZE;
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viapar->shared->cursor_vram_addr = viapar->fbmem_free;
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viapar->fbmem_used += CURSOR_SIZE;
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viapar->fbmem_free -= VQ_SIZE;
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viapar->shared->vq_vram_addr = viapar->fbmem_free;
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viapar->fbmem_used += VQ_SIZE;
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#if defined(CONFIG_VIDEO_VIA_CAMERA) || defined(CONFIG_VIDEO_VIA_CAMERA_MODULE)
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/*
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* Set aside a chunk of framebuffer memory for the camera
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* driver. Someday this driver probably needs a proper allocator
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* for fbmem; for now, we just have to do this before the
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* framebuffer initializes itself.
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*
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* As for the size: the engine can handle three frames,
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* 16 bits deep, up to VGA resolution.
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*/
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viapar->shared->vdev->camera_fbmem_size = 3*VGA_HEIGHT*VGA_WIDTH*2;
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viapar->fbmem_free -= viapar->shared->vdev->camera_fbmem_size;
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viapar->fbmem_used += viapar->shared->vdev->camera_fbmem_size;
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viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free;
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#endif
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viafb_reset_engine(viapar);
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return 0;
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}
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void viafb_reset_engine(struct viafb_par *viapar)
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{
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void __iomem *engine = viapar->shared->vdev->engine_mmio;
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int highest_reg, i;
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u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
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vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
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/* Initialize registers to reset the 2D engine */
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switch (viapar->shared->chip_info.twod_engine) {
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case VIA_2D_ENG_M1:
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highest_reg = 0x5c;
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break;
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default:
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highest_reg = 0x40;
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break;
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}
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for (i = 0; i <= highest_reg; i += 4)
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writel(0x0, engine + i);
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/* Init AGP and VQ regs */
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switch (chip_name) {
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case UNICHROME_K8M890:
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case UNICHROME_P4M900:
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case UNICHROME_VX800:
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case UNICHROME_VX855:
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case UNICHROME_VX900:
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writel(0x00100000, engine + VIA_REG_CR_TRANSET);
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writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
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writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
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break;
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default:
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writel(0x00100000, engine + VIA_REG_TRANSET);
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writel(0x00000000, engine + VIA_REG_TRANSPACE);
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writel(0x00333004, engine + VIA_REG_TRANSPACE);
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writel(0x60000000, engine + VIA_REG_TRANSPACE);
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writel(0x61000000, engine + VIA_REG_TRANSPACE);
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writel(0x62000000, engine + VIA_REG_TRANSPACE);
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writel(0x63000000, engine + VIA_REG_TRANSPACE);
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writel(0x64000000, engine + VIA_REG_TRANSPACE);
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writel(0x7D000000, engine + VIA_REG_TRANSPACE);
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writel(0xFE020000, engine + VIA_REG_TRANSET);
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writel(0x00000000, engine + VIA_REG_TRANSPACE);
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break;
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}
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/* Enable VQ */
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vq_start_addr = viapar->shared->vq_vram_addr;
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vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
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vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
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vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
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vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
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((vq_end_addr & 0xFF000000) >> 16);
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vq_len = 0x53000000 | (VQ_SIZE >> 3);
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switch (chip_name) {
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case UNICHROME_K8M890:
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case UNICHROME_P4M900:
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case UNICHROME_VX800:
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case UNICHROME_VX855:
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case UNICHROME_VX900:
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vq_start_low |= 0x20000000;
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vq_end_low |= 0x20000000;
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vq_high |= 0x20000000;
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vq_len |= 0x20000000;
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writel(0x00100000, engine + VIA_REG_CR_TRANSET);
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writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
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writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
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writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
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writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
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writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
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writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
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break;
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default:
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writel(0x00FE0000, engine + VIA_REG_TRANSET);
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writel(0x080003FE, engine + VIA_REG_TRANSPACE);
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writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
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writel(0x0B000260, engine + VIA_REG_TRANSPACE);
|
|
writel(0x0C000274, engine + VIA_REG_TRANSPACE);
|
|
writel(0x0D000264, engine + VIA_REG_TRANSPACE);
|
|
writel(0x0E000000, engine + VIA_REG_TRANSPACE);
|
|
writel(0x0F000020, engine + VIA_REG_TRANSPACE);
|
|
writel(0x1000027E, engine + VIA_REG_TRANSPACE);
|
|
writel(0x110002FE, engine + VIA_REG_TRANSPACE);
|
|
writel(0x200F0060, engine + VIA_REG_TRANSPACE);
|
|
|
|
writel(0x00000006, engine + VIA_REG_TRANSPACE);
|
|
writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
|
|
writel(0x44000000, engine + VIA_REG_TRANSPACE);
|
|
writel(0x45080C04, engine + VIA_REG_TRANSPACE);
|
|
writel(0x46800408, engine + VIA_REG_TRANSPACE);
|
|
|
|
writel(vq_high, engine + VIA_REG_TRANSPACE);
|
|
writel(vq_start_low, engine + VIA_REG_TRANSPACE);
|
|
writel(vq_end_low, engine + VIA_REG_TRANSPACE);
|
|
writel(vq_len, engine + VIA_REG_TRANSPACE);
|
|
break;
|
|
}
|
|
|
|
/* Set Cursor Image Base Address */
|
|
writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
|
|
writel(0x0, engine + VIA_REG_CURSOR_POS);
|
|
writel(0x0, engine + VIA_REG_CURSOR_ORG);
|
|
writel(0x0, engine + VIA_REG_CURSOR_BG);
|
|
writel(0x0, engine + VIA_REG_CURSOR_FG);
|
|
return;
|
|
}
|
|
|
|
void viafb_show_hw_cursor(struct fb_info *info, int Status)
|
|
{
|
|
struct viafb_par *viapar = info->par;
|
|
u32 temp, iga_path = viapar->iga_path;
|
|
|
|
temp = readl(viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
|
|
switch (Status) {
|
|
case HW_Cursor_ON:
|
|
temp |= 0x1;
|
|
break;
|
|
case HW_Cursor_OFF:
|
|
temp &= 0xFFFFFFFE;
|
|
break;
|
|
}
|
|
switch (iga_path) {
|
|
case IGA2:
|
|
temp |= 0x80000000;
|
|
break;
|
|
case IGA1:
|
|
default:
|
|
temp &= 0x7FFFFFFF;
|
|
}
|
|
writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
|
|
}
|
|
|
|
void viafb_wait_engine_idle(struct fb_info *info)
|
|
{
|
|
struct viafb_par *viapar = info->par;
|
|
int loop = 0;
|
|
u32 mask;
|
|
void __iomem *engine = viapar->shared->vdev->engine_mmio;
|
|
|
|
switch (viapar->shared->chip_info.twod_engine) {
|
|
case VIA_2D_ENG_H5:
|
|
case VIA_2D_ENG_M1:
|
|
mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
|
|
VIA_3D_ENG_BUSY_M1;
|
|
break;
|
|
default:
|
|
while (!(readl(engine + VIA_REG_STATUS) &
|
|
VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
|
|
loop++;
|
|
cpu_relax();
|
|
}
|
|
mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
|
|
break;
|
|
}
|
|
|
|
while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) {
|
|
loop++;
|
|
cpu_relax();
|
|
}
|
|
|
|
if (loop >= MAXLOOP)
|
|
printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
|
|
}
|