mirror of https://gitee.com/openkylin/linux.git
704 lines
15 KiB
ArmAsm
704 lines
15 KiB
ArmAsm
/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
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* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/kexec.h>
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#include <asm/ptrace.h>
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#include <asm/mmu.h>
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.text
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_GLOBAL(call_do_softirq)
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mflr r0
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std r0,16(r1)
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stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
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mr r1,r3
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bl __do_softirq
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ld r1,0(r1)
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ld r0,16(r1)
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mtlr r0
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blr
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_GLOBAL(call_do_irq)
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mflr r0
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std r0,16(r1)
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stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
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mr r1,r4
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bl __do_irq
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ld r1,0(r1)
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ld r0,16(r1)
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mtlr r0
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blr
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.section ".toc","aw"
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PPC64_CACHES:
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.tc ppc64_caches[TC],ppc64_caches
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.section ".text"
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start through stop-1 inclusive
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*/
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_KPROBE(flush_icache_range)
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BEGIN_FTR_SECTION
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PURGE_PREFETCHED_INS
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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* and in some cases i-cache and d-cache line sizes differ from
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* each other.
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*/
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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1: dcbst 0,r6
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add r6,r6,r7
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bdnz 1b
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sync
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/* Now invalidate the instruction cache */
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lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5
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lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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2: icbi 0,r6
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add r6,r6,r7
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bdnz 2b
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isync
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blr
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.previous .text
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/*
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* Like above, but only do the D-cache.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start to stop-1 inclusive
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*/
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_GLOBAL(flush_dcache_range)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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*/
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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0: dcbst 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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blr
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/*
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* Like above, but works on non-mapped physical addresses.
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* Use only for non-LPAR setups ! It also assumes real mode
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* is cacheable. Used for flushing out the DART before using
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* it as uncacheable memory
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*
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* flush_dcache_phys_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start to stop-1 inclusive
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*/
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_GLOBAL(flush_dcache_phys_range)
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mfmsr r5 /* Disable MMU Data Relocation */
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ori r0,r5,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsr r0
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sync
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isync
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mtctr r8
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0: dcbst 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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isync
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mtmsr r5 /* Re-enable MMU Data Relocation */
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sync
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isync
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blr
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_GLOBAL(flush_inval_dcache_range)
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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sync
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isync
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mtctr r8
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0: dcbf 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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isync
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blr
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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*
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* void __flush_dcache_icache(void *page)
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*/
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_GLOBAL(__flush_dcache_icache)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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*/
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BEGIN_FTR_SECTION
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PURGE_PREFETCHED_INS
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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/* Flush the dcache */
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ld r7,PPC64_CACHES@toc(r2)
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clrrdi r3,r3,PAGE_SHIFT /* Page align */
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lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
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lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
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mr r6,r3
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mtctr r4
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0: dcbst 0,r6
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add r6,r6,r5
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bdnz 0b
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sync
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/* Now invalidate the icache */
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lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
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lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
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mtctr r4
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1: icbi 0,r3
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add r3,r3,r5
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bdnz 1b
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isync
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blr
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_GLOBAL(__bswapdi2)
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srdi r8,r3,32
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rlwinm r7,r3,8,0xffffffff
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rlwimi r7,r3,24,0,7
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rlwinm r9,r8,8,0xffffffff
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rlwimi r7,r3,24,16,23
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rlwimi r9,r8,24,0,7
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rlwimi r9,r8,24,16,23
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sldi r7,r7,32
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or r3,r7,r9
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blr
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#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
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_GLOBAL(rmci_on)
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sync
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isync
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li r3,0x100
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rldicl r3,r3,32,0
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mfspr r5,SPRN_HID4
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or r5,r5,r3
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sync
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mtspr SPRN_HID4,r5
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isync
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slbia
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isync
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sync
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blr
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_GLOBAL(rmci_off)
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sync
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isync
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li r3,0x100
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rldicl r3,r3,32,0
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mfspr r5,SPRN_HID4
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andc r5,r5,r3
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sync
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mtspr SPRN_HID4,r5
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isync
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slbia
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isync
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sync
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blr
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#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
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#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
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/*
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* Do an IO access in real mode
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*/
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_GLOBAL(real_readb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsrd r0
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sync
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isync
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mfspr r6,SPRN_HID4
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rldicl r5,r6,32,0
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ori r5,r5,0x100
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rldicl r5,r5,32,0
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sync
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mtspr SPRN_HID4,r5
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isync
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slbia
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isync
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lbz r3,0(r3)
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sync
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mtspr SPRN_HID4,r6
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isync
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slbia
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isync
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mtmsrd r7
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sync
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isync
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blr
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/*
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* Do an IO access in real mode
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*/
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_GLOBAL(real_writeb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsrd r0
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sync
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isync
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mfspr r6,SPRN_HID4
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rldicl r5,r6,32,0
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ori r5,r5,0x100
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rldicl r5,r5,32,0
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sync
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mtspr SPRN_HID4,r5
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isync
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slbia
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isync
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stb r3,0(r4)
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sync
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mtspr SPRN_HID4,r6
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isync
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slbia
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isync
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mtmsrd r7
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sync
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isync
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blr
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#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
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#ifdef CONFIG_PPC_PASEMI
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_GLOBAL(real_205_readb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsrd r0
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sync
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isync
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LBZCIX(R3,R0,R3)
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isync
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mtmsrd r7
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sync
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isync
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blr
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_GLOBAL(real_205_writeb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsrd r0
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sync
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isync
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STBCIX(R3,R0,R4)
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isync
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mtmsrd r7
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sync
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isync
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blr
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#endif /* CONFIG_PPC_PASEMI */
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#if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
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/*
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* SCOM access functions for 970 (FX only for now)
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*
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* unsigned long scom970_read(unsigned int address);
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* void scom970_write(unsigned int address, unsigned long value);
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*
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* The address passed in is the 24 bits register address. This code
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* is 970 specific and will not check the status bits, so you should
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* know what you are doing.
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*/
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_GLOBAL(scom970_read)
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/* interrupts off */
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mfmsr r4
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ori r0,r4,MSR_EE
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xori r0,r0,MSR_EE
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mtmsrd r0,1
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/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
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* (including parity). On current CPUs they must be 0'd,
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* and finally or in RW bit
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*/
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rlwinm r3,r3,8,0,15
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ori r3,r3,0x8000
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/* do the actual scom read */
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sync
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mtspr SPRN_SCOMC,r3
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isync
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mfspr r3,SPRN_SCOMD
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isync
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mfspr r0,SPRN_SCOMC
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isync
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/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
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* that's the best we can do). Not implemented yet as we don't use
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* the scom on any of the bogus CPUs yet, but may have to be done
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* ultimately
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*/
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/* restore interrupts */
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mtmsrd r4,1
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blr
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_GLOBAL(scom970_write)
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/* interrupts off */
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mfmsr r5
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ori r0,r5,MSR_EE
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xori r0,r0,MSR_EE
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mtmsrd r0,1
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/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
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* (including parity). On current CPUs they must be 0'd.
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*/
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rlwinm r3,r3,8,0,15
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sync
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mtspr SPRN_SCOMD,r4 /* write data */
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isync
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mtspr SPRN_SCOMC,r3 /* write command */
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isync
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mfspr 3,SPRN_SCOMC
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isync
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/* restore interrupts */
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mtmsrd r5,1
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blr
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#endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
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/* kexec_wait(phys_cpu)
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*
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* wait for the flag to change, indicating this kernel is going away but
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* the slave code for the next one is at addresses 0 to 100.
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*
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* This is used by all slaves, even those that did not find a matching
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* paca in the secondary startup code.
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*
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* Physical (hardware) cpu id should be in r3.
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*/
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_GLOBAL(kexec_wait)
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bl 1f
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1: mflr r5
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addi r5,r5,kexec_flag-1b
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99: HMT_LOW
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#ifdef CONFIG_KEXEC /* use no memory without kexec */
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lwz r4,0(r5)
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cmpwi 0,r4,0
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beq 99b
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#ifdef CONFIG_PPC_BOOK3S_64
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li r10,0x60
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mfmsr r11
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clrrdi r11,r11,1 /* Clear MSR_LE */
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mtsrr0 r10
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mtsrr1 r11
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rfid
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#else
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/* Create TLB entry in book3e_secondary_core_init */
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li r4,0
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ba 0x60
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#endif
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#endif
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/* this can be in text because we won't change it until we are
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* running in real anyways
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*/
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kexec_flag:
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.long 0
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#ifdef CONFIG_KEXEC
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#ifdef CONFIG_PPC_BOOK3E
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/*
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* BOOK3E has no real MMU mode, so we have to setup the initial TLB
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* for a core to identity map v:0 to p:0. This current implementation
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* assumes that 1G is enough for kexec.
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*/
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kexec_create_tlb:
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/*
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* Invalidate all non-IPROT TLB entries to avoid any TLB conflict.
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* IPROT TLB entries should be >= PAGE_OFFSET and thus not conflict.
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*/
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PPC_TLBILX_ALL(0,R0)
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sync
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isync
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mfspr r10,SPRN_TLB1CFG
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andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */
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subi r10,r10,1 /* Last entry: no conflict with kernel text */
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lis r9,MAS0_TLBSEL(1)@h
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rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */
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/* Set up a temp identity mapping v:0 to p:0 and return to it. */
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#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
|
|
#define M_IF_NEEDED MAS2_M
|
|
#else
|
|
#define M_IF_NEEDED 0
|
|
#endif
|
|
mtspr SPRN_MAS0,r9
|
|
|
|
lis r9,(MAS1_VALID|MAS1_IPROT)@h
|
|
ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
|
|
mtspr SPRN_MAS1,r9
|
|
|
|
LOAD_REG_IMMEDIATE(r9, 0x0 | M_IF_NEEDED)
|
|
mtspr SPRN_MAS2,r9
|
|
|
|
LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
|
|
mtspr SPRN_MAS3,r9
|
|
li r9,0
|
|
mtspr SPRN_MAS7,r9
|
|
|
|
tlbwe
|
|
isync
|
|
blr
|
|
#endif
|
|
|
|
/* kexec_smp_wait(void)
|
|
*
|
|
* call with interrupts off
|
|
* note: this is a terminal routine, it does not save lr
|
|
*
|
|
* get phys id from paca
|
|
* switch to real mode
|
|
* mark the paca as no longer used
|
|
* join other cpus in kexec_wait(phys_id)
|
|
*/
|
|
_GLOBAL(kexec_smp_wait)
|
|
lhz r3,PACAHWCPUID(r13)
|
|
bl real_mode
|
|
|
|
li r4,KEXEC_STATE_REAL_MODE
|
|
stb r4,PACAKEXECSTATE(r13)
|
|
SYNC
|
|
|
|
b kexec_wait
|
|
|
|
/*
|
|
* switch to real mode (turn mmu off)
|
|
* we use the early kernel trick that the hardware ignores bits
|
|
* 0 and 1 (big endian) of the effective address in real mode
|
|
*
|
|
* don't overwrite r3 here, it is live for kexec_wait above.
|
|
*/
|
|
real_mode: /* assume normal blr return */
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
/* Create an identity mapping. */
|
|
b kexec_create_tlb
|
|
#else
|
|
1: li r9,MSR_RI
|
|
li r10,MSR_DR|MSR_IR
|
|
mflr r11 /* return address to SRR0 */
|
|
mfmsr r12
|
|
andc r9,r12,r9
|
|
andc r10,r12,r10
|
|
|
|
mtmsrd r9,1
|
|
mtspr SPRN_SRR1,r10
|
|
mtspr SPRN_SRR0,r11
|
|
rfid
|
|
#endif
|
|
|
|
/*
|
|
* kexec_sequence(newstack, start, image, control, clear_all())
|
|
*
|
|
* does the grungy work with stack switching and real mode switches
|
|
* also does simple calls to other code
|
|
*/
|
|
|
|
_GLOBAL(kexec_sequence)
|
|
mflr r0
|
|
std r0,16(r1)
|
|
|
|
/* switch stacks to newstack -- &kexec_stack.stack */
|
|
stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
|
|
mr r1,r3
|
|
|
|
li r0,0
|
|
std r0,16(r1)
|
|
|
|
/* save regs for local vars on new stack.
|
|
* yes, we won't go back, but ...
|
|
*/
|
|
std r31,-8(r1)
|
|
std r30,-16(r1)
|
|
std r29,-24(r1)
|
|
std r28,-32(r1)
|
|
std r27,-40(r1)
|
|
std r26,-48(r1)
|
|
std r25,-56(r1)
|
|
|
|
stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
|
|
|
|
/* save args into preserved regs */
|
|
mr r31,r3 /* newstack (both) */
|
|
mr r30,r4 /* start (real) */
|
|
mr r29,r5 /* image (virt) */
|
|
mr r28,r6 /* control, unused */
|
|
mr r27,r7 /* clear_all() fn desc */
|
|
mr r26,r8 /* spare */
|
|
lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
|
|
|
|
/* disable interrupts, we are overwriting kernel data next */
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
wrteei 0
|
|
#else
|
|
mfmsr r3
|
|
rlwinm r3,r3,0,17,15
|
|
mtmsrd r3,1
|
|
#endif
|
|
|
|
/* copy dest pages, flush whole dest image */
|
|
mr r3,r29
|
|
bl kexec_copy_flush /* (image) */
|
|
|
|
/* turn off mmu */
|
|
bl real_mode
|
|
|
|
/* copy 0x100 bytes starting at start to 0 */
|
|
li r3,0
|
|
mr r4,r30 /* start, aka phys mem offset */
|
|
li r5,0x100
|
|
li r6,0
|
|
bl copy_and_flush /* (dest, src, copy limit, start offset) */
|
|
1: /* assume normal blr return */
|
|
|
|
/* release other cpus to the new kernel secondary start at 0x60 */
|
|
mflr r5
|
|
li r6,1
|
|
stw r6,kexec_flag-1b(5)
|
|
|
|
#ifndef CONFIG_PPC_BOOK3E
|
|
/* clear out hardware hash page table and tlb */
|
|
#ifdef PPC64_ELF_ABI_v1
|
|
ld r12,0(r27) /* deref function descriptor */
|
|
#else
|
|
mr r12,r27
|
|
#endif
|
|
mtctr r12
|
|
bctrl /* ppc_md.hpte_clear_all(void); */
|
|
#endif /* !CONFIG_PPC_BOOK3E */
|
|
|
|
/*
|
|
* kexec image calling is:
|
|
* the first 0x100 bytes of the entry point are copied to 0
|
|
*
|
|
* all slaves branch to slave = 0x60 (absolute)
|
|
* slave(phys_cpu_id);
|
|
*
|
|
* master goes to start = entry point
|
|
* start(phys_cpu_id, start, 0);
|
|
*
|
|
*
|
|
* a wrapper is needed to call existing kernels, here is an approximate
|
|
* description of one method:
|
|
*
|
|
* v2: (2.6.10)
|
|
* start will be near the boot_block (maybe 0x100 bytes before it?)
|
|
* it will have a 0x60, which will b to boot_block, where it will wait
|
|
* and 0 will store phys into struct boot-block and load r3 from there,
|
|
* copy kernel 0-0x100 and tell slaves to back down to 0x60 again
|
|
*
|
|
* v1: (2.6.9)
|
|
* boot block will have all cpus scanning device tree to see if they
|
|
* are the boot cpu ?????
|
|
* other device tree differences (prop sizes, va vs pa, etc)...
|
|
*/
|
|
mr r3,r25 # my phys cpu
|
|
mr r4,r30 # start, aka phys mem offset
|
|
mtlr 4
|
|
li r5,0
|
|
blr /* image->start(physid, image->start, 0); */
|
|
#endif /* CONFIG_KEXEC */
|