mirror of https://gitee.com/openkylin/linux.git
468 lines
11 KiB
C
468 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Hardware modules present on the OMAP54xx chips
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
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*
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* Paul Walmsley
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* Benoit Cousson
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*/
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#include <linux/io.h>
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#include <linux/power/smartreflex.h>
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#include "omap_hwmod.h"
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#include "omap_hwmod_common_data.h"
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#include "cm1_54xx.h"
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#include "cm2_54xx.h"
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#include "prm54xx.h"
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/* Base offset for all OMAP5 interrupts external to MPUSS */
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#define OMAP54XX_IRQ_GIC_START 32
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/*
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* IP blocks
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*/
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/*
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* 'dmm' class
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* instance(s): dmm
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*/
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static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
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.name = "dmm",
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};
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/* dmm */
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static struct omap_hwmod omap54xx_dmm_hwmod = {
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.name = "dmm",
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.class = &omap54xx_dmm_hwmod_class,
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.clkdm_name = "emif_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'l3' class
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* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
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*/
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static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
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.name = "l3",
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};
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/* l3_instr */
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static struct omap_hwmod omap54xx_l3_instr_hwmod = {
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.name = "l3_instr",
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.class = &omap54xx_l3_hwmod_class,
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.clkdm_name = "l3instr_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/* l3_main_1 */
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static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
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.name = "l3_main_1",
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.class = &omap54xx_l3_hwmod_class,
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.clkdm_name = "l3main1_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
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},
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},
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};
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/* l3_main_2 */
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static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
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.name = "l3_main_2",
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.class = &omap54xx_l3_hwmod_class,
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.clkdm_name = "l3main2_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
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},
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},
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};
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/* l3_main_3 */
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static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
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.name = "l3_main_3",
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.class = &omap54xx_l3_hwmod_class,
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.clkdm_name = "l3instr_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'l4' class
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* instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
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*/
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static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
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.name = "l4",
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};
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/* l4_cfg */
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static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
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.name = "l4_cfg",
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.class = &omap54xx_l4_hwmod_class,
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.clkdm_name = "l4cfg_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
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},
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},
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};
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/* l4_per */
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static struct omap_hwmod omap54xx_l4_per_hwmod = {
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.name = "l4_per",
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.class = &omap54xx_l4_hwmod_class,
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.clkdm_name = "l4per_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
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},
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},
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};
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/* l4_wkup */
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static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &omap54xx_l4_hwmod_class,
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.clkdm_name = "wkupaon_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'mpu_bus' class
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* instance(s): mpu_private
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*/
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static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
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.name = "mpu_bus",
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};
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/* mpu_private */
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static struct omap_hwmod omap54xx_mpu_private_hwmod = {
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.name = "mpu_private",
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.class = &omap54xx_mpu_bus_hwmod_class,
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.clkdm_name = "mpu_clkdm",
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.prcm = {
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.omap4 = {
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/*
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* 'emif' class
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* external memory interface no1 (wrapper)
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*/
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static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
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.rev_offs = 0x0000,
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};
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static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
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.name = "emif",
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.sysc = &omap54xx_emif_sysc,
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};
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/* emif1 */
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static struct omap_hwmod omap54xx_emif1_hwmod = {
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.name = "emif1",
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.class = &omap54xx_emif_hwmod_class,
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.clkdm_name = "emif_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_core_h11x2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/* emif2 */
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static struct omap_hwmod omap54xx_emif2_hwmod = {
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.name = "emif2",
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.class = &omap54xx_emif_hwmod_class,
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.clkdm_name = "emif_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_core_h11x2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'mpu' class
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* mpu sub-system
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*/
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static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
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.name = "mpu",
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};
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/* mpu */
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static struct omap_hwmod omap54xx_mpu_hwmod = {
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.name = "mpu",
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.class = &omap54xx_mpu_hwmod_class,
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.clkdm_name = "mpu_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_mpu_m2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'sata' class
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* sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
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*/
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static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
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.rev_offs = 0x00fc,
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.sysc_offs = 0x0000,
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.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
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.name = "sata",
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.sysc = &omap54xx_sata_sysc,
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};
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/* sata */
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static struct omap_hwmod omap54xx_sata_hwmod = {
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.name = "sata",
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.class = &omap54xx_sata_hwmod_class,
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.clkdm_name = "l3init_clkdm",
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.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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.main_clk = "func_48m_fclk",
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.mpu_rt_idx = 1,
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
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.context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* l4_cfg -> sata */
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static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
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.master = &omap54xx_l4_cfg_hwmod,
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.slave = &omap54xx_sata_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/*
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* Interfaces
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*/
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/* l3_main_1 -> dmm */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
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.master = &omap54xx_l3_main_1_hwmod,
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.slave = &omap54xx_dmm_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_SDMA,
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};
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/* l3_main_3 -> l3_instr */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
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.master = &omap54xx_l3_main_3_hwmod,
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.slave = &omap54xx_l3_instr_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_2 -> l3_main_1 */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
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.master = &omap54xx_l3_main_2_hwmod,
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.slave = &omap54xx_l3_main_1_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_cfg -> l3_main_1 */
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static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
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.master = &omap54xx_l4_cfg_hwmod,
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.slave = &omap54xx_l3_main_1_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* mpu -> l3_main_1 */
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static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
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.master = &omap54xx_mpu_hwmod,
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.slave = &omap54xx_l3_main_1_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU,
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};
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/* l3_main_1 -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
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.master = &omap54xx_l3_main_1_hwmod,
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.slave = &omap54xx_l3_main_2_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU,
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};
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/* l4_cfg -> l3_main_2 */
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static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
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.master = &omap54xx_l4_cfg_hwmod,
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.slave = &omap54xx_l3_main_2_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_1 -> l3_main_3 */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
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.master = &omap54xx_l3_main_1_hwmod,
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.slave = &omap54xx_l3_main_3_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU,
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};
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/* l3_main_2 -> l3_main_3 */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
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.master = &omap54xx_l3_main_2_hwmod,
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.slave = &omap54xx_l3_main_3_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_cfg -> l3_main_3 */
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static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
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.master = &omap54xx_l4_cfg_hwmod,
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.slave = &omap54xx_l3_main_3_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_1 -> l4_cfg */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
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.master = &omap54xx_l3_main_1_hwmod,
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.slave = &omap54xx_l4_cfg_hwmod,
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.clk = "l4_root_clk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_2 -> l4_per */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
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.master = &omap54xx_l3_main_2_hwmod,
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.slave = &omap54xx_l4_per_hwmod,
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.clk = "l4_root_clk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l3_main_1 -> l4_wkup */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
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.master = &omap54xx_l3_main_1_hwmod,
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.slave = &omap54xx_l4_wkup_hwmod,
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.clk = "wkupaon_iclk_mux",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* mpu -> mpu_private */
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static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
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.master = &omap54xx_mpu_hwmod,
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.slave = &omap54xx_mpu_private_hwmod,
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.clk = "l3_iclk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* mpu -> emif1 */
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static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
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.master = &omap54xx_mpu_hwmod,
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.slave = &omap54xx_emif1_hwmod,
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.clk = "dpll_core_h11x2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* mpu -> emif2 */
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static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
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.master = &omap54xx_mpu_hwmod,
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.slave = &omap54xx_emif2_hwmod,
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.clk = "dpll_core_h11x2_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_cfg -> mpu */
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static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
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.master = &omap54xx_l4_cfg_hwmod,
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.slave = &omap54xx_mpu_hwmod,
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.clk = "l4_root_clk_div",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
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&omap54xx_l3_main_1__dmm,
|
|
&omap54xx_l3_main_3__l3_instr,
|
|
&omap54xx_l3_main_2__l3_main_1,
|
|
&omap54xx_l4_cfg__l3_main_1,
|
|
&omap54xx_mpu__l3_main_1,
|
|
&omap54xx_l3_main_1__l3_main_2,
|
|
&omap54xx_l4_cfg__l3_main_2,
|
|
&omap54xx_l3_main_1__l3_main_3,
|
|
&omap54xx_l3_main_2__l3_main_3,
|
|
&omap54xx_l4_cfg__l3_main_3,
|
|
&omap54xx_l3_main_1__l4_cfg,
|
|
&omap54xx_l3_main_2__l4_per,
|
|
&omap54xx_l3_main_1__l4_wkup,
|
|
&omap54xx_mpu__mpu_private,
|
|
&omap54xx_mpu__emif1,
|
|
&omap54xx_mpu__emif2,
|
|
&omap54xx_l4_cfg__mpu,
|
|
&omap54xx_l4_cfg__sata,
|
|
NULL,
|
|
};
|
|
|
|
int __init omap54xx_hwmod_init(void)
|
|
{
|
|
omap_hwmod_init();
|
|
return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
|
|
}
|