openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity
linux/arch/riscv/kernel
History
Greentime Hu 3384b043ea
riscv: fix the IPI missing issue in nommu mode 
This patch fixes the IPI(inner processor interrupt) missing issue. It
failed because it used hartid_mask to iterate for_each_cpu(), however the
cpu_mask and hartid_mask may not be always the same. It will never send the
IPI to hartid 4 because it will be skipped in for_each_cpu loop in my case.

We can reproduce this case in Qemu sifive_u machine by this command.
qemu-system-riscv64 -nographic -smp 5 -m 1G -M sifive_u -kernel \
arch/riscv/boot/loader

It will hang in csd_lock_wait(csd) because the csd_unlock(csd) is not
called. It is not called because hartid 4 doesn't receive the IPI to
release this lock. The caller hart doesn't send the IPI to hartid 4 is
because of hartid 4 is skipped in for_each_cpu(). It will be skipped is
because "(cpu) < nr_cpu_ids" is not true. The hartid is 4 and nr_cpu_ids
is 4. Therefore it should use cpumask in for_each_cpu() instead of
hartid_mask.

        /* Send a message to all CPUs in the map */
        arch_send_call_function_ipi_mask(cfd->cpumask_ipi);

        if (wait) {
                for_each_cpu(cpu, cfd->cpumask) {
                        call_single_data_t *csd;
			csd = per_cpu_ptr(cfd->csd, cpu);
                        csd_lock_wait(csd);
                }
        }

        for ((cpu) = -1;                                \
                (cpu) = cpumask_next((cpu), (mask)),    \
                (cpu) < nr_cpu_ids;)

It could boot to login console after this patch applied.

Fixes: b2d36b5668f6 ("riscv: provide native clint access for M-mode")
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
 		2020-03-18 18:44:39 -07:00
..
vdso riscv: delete temporary files 2020-01-18 13:22:13 -08:00
.gitignore RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00
Makefile riscv: add nommu support 2019-11-17 15:17:39 -08:00
asm-offsets.c riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
cacheinfo.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
clint.c riscv: provide native clint access for M-mode 2019-11-17 15:17:39 -08:00
cpu.c RISC-V: Remove unsupported isa string info print 2019-10-28 11:13:59 -07:00
cpufeature.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
entry.S riscv: fix seccomp reject syscall code path 2020-03-05 13:58:15 -08:00
fpu.S riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
ftrace.c riscv: ftrace: correct the condition logic in function graph tracer 2020-01-03 00:56:37 -08:00
head.S riscv: set pmp configuration if kernel is running in M-mode 2020-02-18 09:41:24 -08:00
head.h riscv: add prototypes for assembly language functions from head.S 2019-10-28 00:46:00 -07:00
irq.c riscv: prefix IRQ_ macro names with an RV_ namespace 2020-01-04 21:48:59 -08:00
mcount-dyn.S riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
mcount.S RISC-V: remove the unused return_to_handler export 2018-10-22 17:38:12 -07:00
module-sections.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
module.c riscv: avoid the PIC offset of static percpu data in module beyond 2G limits 2020-03-03 10:27:45 -08:00
module.lds RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
perf_callchain.c riscv: abstract out CSR names for supervisor vs machine mode 2019-11-05 09:20:42 -08:00
perf_event.c RISC-V: Access CSRs using CSR numbers 2019-05-16 20:42:11 -07:00
perf_regs.c riscv: Add support for perf registers sampling 2019-09-05 00:48:58 -07:00
process.c riscv: Implement copy_thread_tls 2020-01-07 13:31:23 +01:00
ptrace.c riscv: fix seccomp reject syscall code path 2020-03-05 13:58:15 -08:00
reset.c riscv: cleanup the default power off implementation 2019-11-13 13:22:52 -08:00
riscv_ksyms.c riscv: Add KASAN support 2020-01-22 13:09:58 -08:00
sbi.c riscv: cleanup the default power off implementation 2019-11-13 13:22:52 -08:00
setup.c RISC-V Patches for the 5.6 Merge Window, Part 1 2020-01-31 11:23:29 -08:00
signal.c riscv: add nommu support 2019-11-17 15:17:39 -08:00
smp.c riscv: fix the IPI missing issue in nommu mode 2020-03-18 18:44:39 -07:00
smpboot.c riscv: provide native clint access for M-mode 2019-11-17 15:17:39 -08:00
stacktrace.c riscv: Add perf callchain support 2019-09-04 12:43:00 -07:00
sys_riscv.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05 17:36:37 +02:00
syscall_table.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
time.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
traps.c RISC-V: Don't enable all interrupts in trap_init() 2020-02-18 10:34:04 -08:00
vdso.c riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
vmlinux.lds.S riscv: Add KASAN support 2020-01-22 13:09:58 -08:00