mirror of https://gitee.com/openkylin/linux.git
138 lines
4.5 KiB
C
138 lines
4.5 KiB
C
/*
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* arch/arm/mach-lpc32xx/pm.c
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*
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* Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
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* Modified by Kevin Wells <kevin.wells@nxp.com>
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* LPC32XX CPU and system power management
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*
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* The LPC32XX has three CPU modes for controlling system power: run,
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* direct-run, and halt modes. When switching between halt and run modes,
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* the CPU transistions through direct-run mode. For Linux, direct-run
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* mode is not used in normal operation. Halt mode is used when the
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* system is fully suspended.
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*
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* Run mode:
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* The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
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* derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
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* the HCLK_PLL rate. Linux runs in this mode.
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*
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* Direct-run mode:
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* The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
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* SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
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* source or the frequency of the main oscillator. In this mode, the
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* HCLK_PLL can be safely enabled, changed, or disabled.
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*
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* Halt mode:
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* SYSCLK is gated off and the CPU and system clocks are halted.
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* Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
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* key scanner, etc.) still operate if enabled. In this state, an enabled
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* system event (ie, GPIO state change, RTC match, key press, etc.) will
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* wake the system up back into direct-run mode.
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*
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* DRAM refresh
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* DRAM clocking and refresh are slightly different for systems with DDR
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* DRAM or regular SDRAM devices. If SDRAM is used in the system, the
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* SDRAM will still be accessible in direct-run mode. In DDR based systems,
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* a transition to direct-run mode will stop all DDR accesses (no clocks).
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* Because of this, the code to switch power modes and the code to enter
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* and exit DRAM self-refresh modes must not be executed in DRAM. A small
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* section of IRAM is used instead for this.
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*
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* Suspend is handled with the following logic:
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* Backup a small area of IRAM used for the suspend code
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* Copy suspend code to IRAM
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* Transfer control to code in IRAM
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* Places DRAMs in self-refresh mode
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* Enter direct-run mode
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* Save state of HCLK_PLL PLL
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* Disable HCLK_PLL PLL
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* Enter halt mode - CPU and buses will stop
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* System enters direct-run mode when an enabled event occurs
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* HCLK PLL state is restored
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* Run mode is entered
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* DRAMS are placed back into normal mode
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* Code execution returns from IRAM
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* IRAM code are used for suspend is restored
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* Suspend mode is exited
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*/
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#include <linux/suspend.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <asm/cacheflush.h>
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#include "lpc32xx.h"
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#include "common.h"
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#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
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/*
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* Both STANDBY and MEM suspend states are handled the same with no
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* loss of CPU or memory state
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*/
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static int lpc32xx_pm_enter(suspend_state_t state)
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{
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int (*lpc32xx_suspend_ptr) (void);
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void *iram_swap_area;
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/* Allocate some space for temporary IRAM storage */
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iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
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lpc32xx_sys_suspend_sz, GFP_KERNEL);
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if (!iram_swap_area)
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return -ENOMEM;
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/*
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* Copy code to suspend system into IRAM. The suspend code
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* needs to run from IRAM as DRAM may no longer be available
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* when the PLL is stopped.
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*/
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memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
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lpc32xx_sys_suspend_sz);
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flush_icache_range((unsigned long)TEMP_IRAM_AREA,
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(unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
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/* Transfer to suspend code in IRAM */
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lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
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flush_cache_all();
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(void) lpc32xx_suspend_ptr();
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/* Restore original IRAM contents */
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memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
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lpc32xx_sys_suspend_sz);
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kfree(iram_swap_area);
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return 0;
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}
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static const struct platform_suspend_ops lpc32xx_pm_ops = {
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.valid = suspend_valid_only_mem,
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.enter = lpc32xx_pm_enter,
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};
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#define EMC_DYN_MEM_CTRL_OFS 0x20
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#define EMC_SRMMC (1 << 3)
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#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
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static int __init lpc32xx_pm_init(void)
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{
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/*
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* Setup SDRAM self-refresh clock to automatically disable o
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* start of self-refresh. This only needs to be done once.
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*/
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__raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
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suspend_set_ops(&lpc32xx_pm_ops);
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return 0;
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}
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arch_initcall(lpc32xx_pm_init);
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