mirror of https://gitee.com/openkylin/linux.git
507 lines
13 KiB
C
507 lines
13 KiB
C
/*
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* Code to handle IP32 IRQs
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Harald Koerfgen
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* Copyright (C) 2001 Keith M Wesolowski
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*/
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/random.h>
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#include <linux/sched.h>
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#include <asm/mipsregs.h>
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#include <asm/signal.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/ip32/crime.h>
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#include <asm/ip32/mace.h>
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#include <asm/ip32/ip32_ints.h>
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/* issue a PIO read to make sure no PIO writes are pending */
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static void inline flush_crime_bus(void)
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{
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crime->control;
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}
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static void inline flush_mace_bus(void)
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{
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mace->perif.ctrl.misc;
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}
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#undef DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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/* O2 irq map
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*
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* IP0 -> software (ignored)
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* IP1 -> software (ignored)
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* IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
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* IP3 -> (irq1) X unknown
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* IP4 -> (irq2) X unknown
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* IP5 -> (irq3) X unknown
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* IP6 -> (irq4) X unknown
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* IP7 -> (irq5) 0 CPU count/compare timer (system timer)
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*
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* crime: (C)
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*
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* CRIME_INT_STAT 31:0:
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*
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* 0 -> 1 Video in 1
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* 1 -> 2 Video in 2
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* 2 -> 3 Video out
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* 3 -> 4 Mace ethernet
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* 4 -> S SuperIO sub-interrupt
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* 5 -> M Miscellaneous sub-interrupt
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* 6 -> A Audio sub-interrupt
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* 7 -> 8 PCI bridge errors
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* 8 -> 9 PCI SCSI aic7xxx 0
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* 9 -> 10 PCI SCSI aic7xxx 1
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* 10 -> 11 PCI slot 0
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* 11 -> 12 unused (PCI slot 1)
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* 12 -> 13 unused (PCI slot 2)
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* 13 -> 14 unused (PCI shared 0)
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* 14 -> 15 unused (PCI shared 1)
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* 15 -> 16 unused (PCI shared 2)
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* 16 -> 17 GBE0 (E)
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* 17 -> 18 GBE1 (E)
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* 18 -> 19 GBE2 (E)
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* 19 -> 20 GBE3 (E)
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* 20 -> 21 CPU errors
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* 21 -> 22 Memory errors
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* 22 -> 23 RE empty edge (E)
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* 23 -> 24 RE full edge (E)
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* 24 -> 25 RE idle edge (E)
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* 25 -> 26 RE empty level
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* 26 -> 27 RE full level
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* 27 -> 28 RE idle level
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* 28 -> 29 unused (software 0) (E)
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* 29 -> 30 unused (software 1) (E)
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* 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
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* 31 -> 32 VICE
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*
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* S, M, A: Use the MACE ISA interrupt register
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* MACE_ISA_INT_STAT 31:0
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*
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* 0-7 -> 33-40 Audio
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* 8 -> 41 RTC
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* 9 -> 42 Keyboard
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* 10 -> X Keyboard polled
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* 11 -> 44 Mouse
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* 12 -> X Mouse polled
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* 13-15 -> 46-48 Count/compare timers
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* 16-19 -> 49-52 Parallel (16 E)
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* 20-25 -> 53-58 Serial 1 (22 E)
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* 26-31 -> 59-64 Serial 2 (28 E)
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*
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* Note that this means IRQs 5-7, 43, and 45 do not exist. This is a
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* different IRQ map than IRIX uses, but that's OK as Linux irq handling
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* is quite different anyway.
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*/
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/* Some initial interrupts to set up */
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extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
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extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
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struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
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CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
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struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED,
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CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };
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/*
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* For interrupts wired from a single device to the CPU. Only the clock
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* uses this it seems, which is IRQ 0 and IP7.
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*/
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static void enable_cpu_irq(unsigned int irq)
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{
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set_c0_status(STATUSF_IP7);
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}
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static void disable_cpu_irq(unsigned int irq)
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{
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clear_c0_status(STATUSF_IP7);
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}
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static void end_cpu_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_cpu_irq (irq);
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}
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static struct irq_chip ip32_cpu_interrupt = {
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.name = "IP32 CPU",
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.ack = disable_cpu_irq,
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.mask = disable_cpu_irq,
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.mask_ack = disable_cpu_irq,
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.unmask = enable_cpu_irq,
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.end = end_cpu_irq,
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};
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/*
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* This is for pure CRIME interrupts - ie not MACE. The advantage?
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* We get to split the register in half and do faster lookups.
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*/
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static uint64_t crime_mask;
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static void enable_crime_irq(unsigned int irq)
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{
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crime_mask |= 1 << (irq - 1);
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crime->imask = crime_mask;
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}
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static void disable_crime_irq(unsigned int irq)
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{
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crime_mask &= ~(1 << (irq - 1));
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crime->imask = crime_mask;
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flush_crime_bus();
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}
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static void mask_and_ack_crime_irq(unsigned int irq)
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{
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/* Edge triggered interrupts must be cleared. */
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if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
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|| (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
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|| (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
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uint64_t crime_int;
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crime_int = crime->hard_int;
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crime_int &= ~(1 << (irq - 1));
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crime->hard_int = crime_int;
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}
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disable_crime_irq(irq);
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}
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static void end_crime_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_crime_irq(irq);
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}
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static struct irq_chip ip32_crime_interrupt = {
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.name = "IP32 CRIME",
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.ack = mask_and_ack_crime_irq,
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.mask = disable_crime_irq,
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.mask_ack = mask_and_ack_crime_irq,
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.unmask = enable_crime_irq,
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.end = end_crime_irq,
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};
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/*
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* This is for MACE PCI interrupts. We can decrease bus traffic by masking
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* as close to the source as possible. This also means we can take the
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* next chunk of the CRIME register in one piece.
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*/
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static unsigned long macepci_mask;
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static void enable_macepci_irq(unsigned int irq)
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{
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macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
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mace->pci.control = macepci_mask;
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crime_mask |= 1 << (irq - 1);
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crime->imask = crime_mask;
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}
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static void disable_macepci_irq(unsigned int irq)
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{
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crime_mask &= ~(1 << (irq - 1));
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crime->imask = crime_mask;
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flush_crime_bus();
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macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
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mace->pci.control = macepci_mask;
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flush_mace_bus();
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}
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static void end_macepci_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_macepci_irq(irq);
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}
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static struct irq_chip ip32_macepci_interrupt = {
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.name = "IP32 MACE PCI",
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.ack = disable_macepci_irq,
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.mask = disable_macepci_irq,
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.mask_ack = disable_macepci_irq,
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.unmask = enable_macepci_irq,
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.end = end_macepci_irq,
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};
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/* This is used for MACE ISA interrupts. That means bits 4-6 in the
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* CRIME register.
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*/
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#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \
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MACEISA_AUDIO_SC_INT | \
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MACEISA_AUDIO1_DMAT_INT | \
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MACEISA_AUDIO1_OF_INT | \
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MACEISA_AUDIO2_DMAT_INT | \
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MACEISA_AUDIO2_MERR_INT | \
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MACEISA_AUDIO3_DMAT_INT | \
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MACEISA_AUDIO3_MERR_INT)
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#define MACEISA_MISC_INT (MACEISA_RTC_INT | \
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MACEISA_KEYB_INT | \
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MACEISA_KEYB_POLL_INT | \
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MACEISA_MOUSE_INT | \
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MACEISA_MOUSE_POLL_INT | \
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MACEISA_TIMER0_INT | \
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MACEISA_TIMER1_INT | \
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MACEISA_TIMER2_INT)
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#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \
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MACEISA_PAR_CTXA_INT | \
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MACEISA_PAR_CTXB_INT | \
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MACEISA_PAR_MERR_INT | \
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MACEISA_SERIAL1_INT | \
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MACEISA_SERIAL1_TDMAT_INT | \
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MACEISA_SERIAL1_TDMAPR_INT | \
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MACEISA_SERIAL1_TDMAME_INT | \
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MACEISA_SERIAL1_RDMAT_INT | \
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MACEISA_SERIAL1_RDMAOR_INT | \
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MACEISA_SERIAL2_INT | \
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MACEISA_SERIAL2_TDMAT_INT | \
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MACEISA_SERIAL2_TDMAPR_INT | \
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MACEISA_SERIAL2_TDMAME_INT | \
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MACEISA_SERIAL2_RDMAT_INT | \
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MACEISA_SERIAL2_RDMAOR_INT)
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static unsigned long maceisa_mask;
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static void enable_maceisa_irq (unsigned int irq)
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{
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unsigned int crime_int = 0;
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DBG ("maceisa enable: %u\n", irq);
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switch (irq) {
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case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
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crime_int = MACE_AUDIO_INT;
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break;
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case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
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crime_int = MACE_MISC_INT;
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break;
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case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
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crime_int = MACE_SUPERIO_INT;
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break;
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}
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DBG ("crime_int %08x enabled\n", crime_int);
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crime_mask |= crime_int;
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crime->imask = crime_mask;
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maceisa_mask |= 1 << (irq - 33);
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mace->perif.ctrl.imask = maceisa_mask;
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}
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static void disable_maceisa_irq(unsigned int irq)
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{
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unsigned int crime_int = 0;
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maceisa_mask &= ~(1 << (irq - 33));
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if(!(maceisa_mask & MACEISA_AUDIO_INT))
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crime_int |= MACE_AUDIO_INT;
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if(!(maceisa_mask & MACEISA_MISC_INT))
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crime_int |= MACE_MISC_INT;
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if(!(maceisa_mask & MACEISA_SUPERIO_INT))
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crime_int |= MACE_SUPERIO_INT;
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crime_mask &= ~crime_int;
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crime->imask = crime_mask;
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flush_crime_bus();
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mace->perif.ctrl.imask = maceisa_mask;
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flush_mace_bus();
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}
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static void mask_and_ack_maceisa_irq(unsigned int irq)
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{
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unsigned long mace_int;
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switch (irq) {
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case MACEISA_PARALLEL_IRQ:
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case MACEISA_SERIAL1_TDMAPR_IRQ:
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case MACEISA_SERIAL2_TDMAPR_IRQ:
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/* edge triggered */
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mace_int = mace->perif.ctrl.istat;
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mace_int &= ~(1 << (irq - 33));
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mace->perif.ctrl.istat = mace_int;
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break;
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}
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disable_maceisa_irq(irq);
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}
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static void end_maceisa_irq(unsigned irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_maceisa_irq(irq);
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}
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static struct irq_chip ip32_maceisa_interrupt = {
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.name = "IP32 MACE ISA",
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.ack = mask_and_ack_maceisa_irq,
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.mask = disable_maceisa_irq,
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.mask_ack = mask_and_ack_maceisa_irq,
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.unmask = enable_maceisa_irq,
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.end = end_maceisa_irq,
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};
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/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
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* bits 0-3 and 7 in the CRIME register.
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*/
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static void enable_mace_irq(unsigned int irq)
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{
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crime_mask |= 1 << (irq - 1);
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crime->imask = crime_mask;
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}
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static void disable_mace_irq(unsigned int irq)
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{
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crime_mask &= ~(1 << (irq - 1));
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crime->imask = crime_mask;
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flush_crime_bus();
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}
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static void end_mace_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_mace_irq(irq);
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}
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static struct irq_chip ip32_mace_interrupt = {
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.name = "IP32 MACE",
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.ack = disable_mace_irq,
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.mask = disable_mace_irq,
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.mask_ack = disable_mace_irq,
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.unmask = enable_mace_irq,
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.end = end_mace_irq,
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};
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static void ip32_unknown_interrupt(void)
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{
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printk ("Unknown interrupt occurred!\n");
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printk ("cp0_status: %08x\n", read_c0_status());
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printk ("cp0_cause: %08x\n", read_c0_cause());
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printk ("CRIME intr mask: %016lx\n", crime->imask);
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printk ("CRIME intr status: %016lx\n", crime->istat);
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printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
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printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
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printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
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printk ("MACE PCI control register: %08x\n", mace->pci.control);
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printk("Register dump:\n");
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show_regs(get_irq_regs());
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printk("Please mail this report to linux-mips@linux-mips.org\n");
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printk("Spinning...");
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while(1) ;
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}
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/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
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/* change this to loop over all edge-triggered irqs, exception masked out ones */
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static void ip32_irq0(void)
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{
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uint64_t crime_int;
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int irq = 0;
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crime_int = crime->istat & crime_mask;
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irq = __ffs(crime_int);
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crime_int = 1 << irq;
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if (crime_int & CRIME_MACEISA_INT_MASK) {
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unsigned long mace_int = mace->perif.ctrl.istat;
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irq = __ffs(mace_int & maceisa_mask) + 32;
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}
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irq++;
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DBG("*irq %u*\n", irq);
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do_IRQ(irq);
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}
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static void ip32_irq1(void)
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{
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ip32_unknown_interrupt();
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}
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static void ip32_irq2(void)
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{
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ip32_unknown_interrupt();
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}
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static void ip32_irq3(void)
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{
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ip32_unknown_interrupt();
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}
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static void ip32_irq4(void)
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{
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ip32_unknown_interrupt();
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}
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static void ip32_irq5(void)
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{
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ll_timer_interrupt(IP32_R4K_TIMER_IRQ);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_cause();
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if (likely(pending & IE_IRQ0))
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ip32_irq0();
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else if (unlikely(pending & IE_IRQ1))
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ip32_irq1();
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else if (unlikely(pending & IE_IRQ2))
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ip32_irq2();
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else if (unlikely(pending & IE_IRQ3))
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ip32_irq3();
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else if (unlikely(pending & IE_IRQ4))
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ip32_irq4();
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else if (likely(pending & IE_IRQ5))
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ip32_irq5();
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}
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void __init arch_init_irq(void)
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{
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unsigned int irq;
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/* Install our interrupt handler, then clear and disable all
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* CRIME and MACE interrupts. */
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crime->imask = 0;
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crime->hard_int = 0;
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crime->soft_int = 0;
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mace->perif.ctrl.istat = 0;
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mace->perif.ctrl.imask = 0;
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for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
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struct irq_chip *controller;
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if (irq == IP32_R4K_TIMER_IRQ)
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controller = &ip32_cpu_interrupt;
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else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
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controller = &ip32_mace_interrupt;
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else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
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controller = &ip32_macepci_interrupt;
|
|
else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
|
|
controller = &ip32_crime_interrupt;
|
|
else
|
|
controller = &ip32_maceisa_interrupt;
|
|
|
|
set_irq_chip(irq, controller);
|
|
}
|
|
setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
|
|
setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
|
|
|
|
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
|
|
change_c0_status(ST0_IM, ALLINTS);
|
|
}
|