mirror of https://gitee.com/openkylin/linux.git
519 lines
14 KiB
C
519 lines
14 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_ras_eeprom.h"
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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#include <linux/bits.h>
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#include "smu_v11_0_i2c.h"
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#define EEPROM_I2C_TARGET_ADDR 0xA0
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/*
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* The 2 macros bellow represent the actual size in bytes that
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* those entities occupy in the EEPROM memory.
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* EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
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* uses uint64 to store 6b fields such as retired_page.
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*/
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#define EEPROM_TABLE_HEADER_SIZE 20
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#define EEPROM_TABLE_RECORD_SIZE 24
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#define EEPROM_ADDRESS_SIZE 0x2
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/* Table hdr is 'AMDR' */
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#define EEPROM_TABLE_HDR_VAL 0x414d4452
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#define EEPROM_TABLE_VER 0x00010000
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/* Assume 2 Mbit size */
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#define EEPROM_SIZE_BYTES 256000
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#define EEPROM_PAGE__SIZE_BYTES 256
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#define EEPROM_HDR_START 0
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#define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
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#define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
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#define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
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#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
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static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr,
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unsigned char *buff)
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{
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uint32_t *pp = (uint32_t *) buff;
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pp[0] = cpu_to_le32(hdr->header);
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pp[1] = cpu_to_le32(hdr->version);
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pp[2] = cpu_to_le32(hdr->first_rec_offset);
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pp[3] = cpu_to_le32(hdr->tbl_size);
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pp[4] = cpu_to_le32(hdr->checksum);
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}
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static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr,
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unsigned char *buff)
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{
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uint32_t *pp = (uint32_t *)buff;
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hdr->header = le32_to_cpu(pp[0]);
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hdr->version = le32_to_cpu(pp[1]);
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hdr->first_rec_offset = le32_to_cpu(pp[2]);
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hdr->tbl_size = le32_to_cpu(pp[3]);
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hdr->checksum = le32_to_cpu(pp[4]);
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}
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static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
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unsigned char *buff)
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{
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int ret = 0;
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struct i2c_msg msg = {
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.addr = EEPROM_I2C_TARGET_ADDR,
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.flags = 0,
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.len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
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.buf = buff,
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};
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*(uint16_t *)buff = EEPROM_HDR_START;
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__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
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ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
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if (ret < 1)
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DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
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return ret;
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}
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static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
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{
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int i;
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uint32_t tbl_sum = 0;
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/* Header checksum, skip checksum field in the calculation */
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for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
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tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
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return tbl_sum;
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}
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static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records,
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int num)
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{
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int i, j;
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uint32_t tbl_sum = 0;
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/* Records checksum */
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for (i = 0; i < num; i++) {
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struct eeprom_table_record *record = &records[i];
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for (j = 0; j < sizeof(*record); j++) {
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tbl_sum += *(((unsigned char *)record) + j);
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}
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}
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return tbl_sum;
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}
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static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *records, int num)
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{
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return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
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}
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/* Checksum = 256 -((sum of all table entries) mod 256) */
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static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *records, int num,
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uint32_t old_hdr_byte_sum)
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{
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/*
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* This will update the table sum with new records.
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*
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* TODO: What happens when the EEPROM table is to be wrapped around
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* and old records from start will get overridden.
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*/
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/* need to recalculate updated header byte sum */
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control->tbl_byte_sum -= old_hdr_byte_sum;
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control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
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control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
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}
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/* table sum mod 256 + checksum must equals 256 */
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static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *records, int num)
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{
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control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
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if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
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DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
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return false;
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}
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return true;
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}
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int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
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{
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unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
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struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
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int ret = 0;
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mutex_lock(&control->tbl_mutex);
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hdr->header = EEPROM_TABLE_HDR_VAL;
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hdr->version = EEPROM_TABLE_VER;
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hdr->first_rec_offset = EEPROM_RECORD_START;
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hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
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control->tbl_byte_sum = 0;
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__update_tbl_checksum(control, NULL, 0, 0);
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control->next_addr = EEPROM_RECORD_START;
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ret = __update_table_header(control, buff);
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mutex_unlock(&control->tbl_mutex);
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return ret;
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}
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int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
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{
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int ret = 0;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
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struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
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struct i2c_msg msg = {
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.addr = EEPROM_I2C_TARGET_ADDR,
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.flags = I2C_M_RD,
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.len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
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.buf = buff,
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};
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mutex_init(&control->tbl_mutex);
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
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break;
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case CHIP_ARCTURUS:
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ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
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break;
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default:
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return 0;
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}
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if (ret) {
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DRM_ERROR("Failed to init I2C controller, ret:%d", ret);
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return ret;
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}
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/* Read/Create table header from EEPROM address 0 */
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ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
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if (ret < 1) {
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DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
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return ret;
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}
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__decode_table_header_from_buff(hdr, &buff[2]);
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if (hdr->header == EEPROM_TABLE_HDR_VAL) {
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control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
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EEPROM_TABLE_RECORD_SIZE;
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control->tbl_byte_sum = __calc_hdr_byte_sum(control);
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control->next_addr = EEPROM_RECORD_START;
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DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
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control->num_recs);
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} else {
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DRM_INFO("Creating new EEPROM table");
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ret = amdgpu_ras_eeprom_reset_table(control);
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}
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return ret == 1 ? 0 : -EIO;
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}
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void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)
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{
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struct amdgpu_device *adev = to_amdgpu_device(control);
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);
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break;
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case CHIP_ARCTURUS:
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smu_i2c_eeprom_fini(&adev->smu, &control->eeprom_accessor);
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break;
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default:
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return;
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}
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}
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static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *record,
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unsigned char *buff)
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{
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__le64 tmp = 0;
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int i = 0;
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/* Next are all record fields according to EEPROM page spec in LE foramt */
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buff[i++] = record->err_type;
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buff[i++] = record->bank;
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tmp = cpu_to_le64(record->ts);
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memcpy(buff + i, &tmp, 8);
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i += 8;
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tmp = cpu_to_le64((record->offset & 0xffffffffffff));
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memcpy(buff + i, &tmp, 6);
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i += 6;
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buff[i++] = record->mem_channel;
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buff[i++] = record->mcumc_id;
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tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
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memcpy(buff + i, &tmp, 6);
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}
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static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *record,
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unsigned char *buff)
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{
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__le64 tmp = 0;
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int i = 0;
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/* Next are all record fields according to EEPROM page spec in LE foramt */
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record->err_type = buff[i++];
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record->bank = buff[i++];
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memcpy(&tmp, buff + i, 8);
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record->ts = le64_to_cpu(tmp);
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i += 8;
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memcpy(&tmp, buff + i, 6);
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record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
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i += 6;
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record->mem_channel = buff[i++];
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record->mcumc_id = buff[i++];
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memcpy(&tmp, buff + i, 6);
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record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
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}
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/*
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* When reaching end of EEPROM memory jump back to 0 record address
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* When next record access will go beyond EEPROM page boundary modify bits A17/A8
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* in I2C selector to go to next page
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*/
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static uint32_t __correct_eeprom_dest_address(uint32_t curr_address)
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{
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uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE;
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/* When all EEPROM memory used jump back to 0 address */
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if (next_address > EEPROM_SIZE_BYTES) {
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DRM_INFO("Reached end of EEPROM memory, jumping to 0 "
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"and overriding old record");
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return EEPROM_RECORD_START;
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}
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/*
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* To check if we overflow page boundary compare next address with
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* current and see if bits 17/8 of the EEPROM address will change
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* If they do start from the next 256b page
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*
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* https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2
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*/
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if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) {
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DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx",
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(next_address & EEPROM_ADDR_MSB_MASK));
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return (next_address & EEPROM_ADDR_MSB_MASK);
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}
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return curr_address;
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}
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int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *records,
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bool write,
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int num)
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{
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int i, ret = 0;
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struct i2c_msg *msgs, *msg;
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unsigned char *buffs, *buff;
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struct eeprom_table_record *record;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
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return 0;
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buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
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GFP_KERNEL);
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if (!buffs)
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return -ENOMEM;
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mutex_lock(&control->tbl_mutex);
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msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL);
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if (!msgs) {
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ret = -ENOMEM;
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goto free_buff;
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}
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/* In case of overflow just start from beginning to not lose newest records */
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if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES))
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control->next_addr = EEPROM_RECORD_START;
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/*
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* TODO Currently makes EEPROM writes for each record, this creates
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* internal fragmentation. Optimized the code to do full page write of
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* 256b
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*/
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for (i = 0; i < num; i++) {
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buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
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record = &records[i];
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msg = &msgs[i];
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control->next_addr = __correct_eeprom_dest_address(control->next_addr);
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/*
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* Update bits 16,17 of EEPROM address in I2C address by setting them
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* to bits 1,2 of Device address byte
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*/
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msg->addr = EEPROM_I2C_TARGET_ADDR |
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((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
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msg->flags = write ? 0 : I2C_M_RD;
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msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
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msg->buf = buff;
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/* Insert the EEPROM dest addess, bits 0-15 */
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buff[0] = ((control->next_addr >> 8) & 0xff);
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buff[1] = (control->next_addr & 0xff);
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/* EEPROM table content is stored in LE format */
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if (write)
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__encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
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/*
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* The destination EEPROM address might need to be corrected to account
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* for page or entire memory wrapping
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*/
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control->next_addr += EEPROM_TABLE_RECORD_SIZE;
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}
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ret = i2c_transfer(&control->eeprom_accessor, msgs, num);
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if (ret < 1) {
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DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret);
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/* TODO Restore prev next EEPROM address ? */
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goto free_msgs;
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}
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if (!write) {
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for (i = 0; i < num; i++) {
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buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
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record = &records[i];
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__decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
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}
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}
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if (write) {
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uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);
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/*
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* Update table header with size and CRC and account for table
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* wrap around where the assumption is that we treat it as empty
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* table
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*
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* TODO - Check the assumption is correct
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*/
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control->num_recs += num;
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control->num_recs %= EEPROM_MAX_RECORD_NUM;
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control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num;
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if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES)
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control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE +
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control->num_recs * EEPROM_TABLE_RECORD_SIZE;
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__update_tbl_checksum(control, records, num, old_hdr_byte_sum);
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__update_table_header(control, buffs);
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} else if (!__validate_tbl_checksum(control, records, num)) {
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DRM_WARN("EEPROM Table checksum mismatch!");
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/* TODO Uncomment when EEPROM read/write is relliable */
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/* ret = -EIO; */
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}
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free_msgs:
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kfree(msgs);
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free_buff:
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kfree(buffs);
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mutex_unlock(&control->tbl_mutex);
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return ret == num ? 0 : -EIO;
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}
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/* Used for testing if bugs encountered */
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#if 0
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void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control)
|
||
{
|
||
int i;
|
||
struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL);
|
||
|
||
if (!recs)
|
||
return;
|
||
|
||
for (i = 0; i < 1 ; i++) {
|
||
recs[i].address = 0xdeadbeef;
|
||
recs[i].retired_page = i;
|
||
}
|
||
|
||
if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
|
||
|
||
memset(recs, 0, sizeof(*recs) * 1);
|
||
|
||
control->next_addr = EEPROM_RECORD_START;
|
||
|
||
if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) {
|
||
for (i = 0; i < 1; i++)
|
||
DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu",
|
||
recs[i].address, recs[i].retired_page);
|
||
} else
|
||
DRM_ERROR("Failed in reading from table");
|
||
|
||
} else
|
||
DRM_ERROR("Failed in writing to table");
|
||
}
|
||
#endif
|